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A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS

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Abstract

This paper presents a power-efficient successive-approximation register (SAR) analog-to-digital converter (ADC) with fast response reference buffer (RV-buffer). Several techniques are applied in the system design to improve the performance of the SAR ADC. A novel timing-redistribution SAR logic is proposed to balance the difference between required settling time for the most significant bit and the least significant bits (LSBs) in the digital-to-analog capacitor array, which reduces the incomplete settling error and releases the requirements on the RV-buffer to achieve lower power dissipation. The SAR ADC is fabricated in 40-nm CMOS technology occupying 0.13 mm\(^{2}\) area. At 1.1 V supply voltage and 80 MHz sampling frequency, the ADC achieves 50.7 dB SNDR, 69.5 dBc SFDR with a 1 MHz input at −8 dBFS. The total power consumption of the ADC is 2.99 mW, including the reference buffer power consumption of 2 mW. The Schreier FoM is 164.1 dB.

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Acknowledgements

We would like to thank the Chinese National Nature Science Foundation (No. 61974092) for funding this research.

Funding

Chinese National Nature Science Foundation (No. 61974092)

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Authors and Affiliations

  1. Center for Analog/RF Integrated Circuits (CARFIC), Department of Micro/Nano Electronics, Shanghai Jiao Tong University, Shanghai, 200240, China

    Mengying Hu, Jing Jin, Yuekang Guo, Xiaoming Liu & Jianjun Zhou

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  1. Mengying Hu
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  3. Yuekang Guo
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Correspondence to Jing Jin.

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Hu, M., Jin, J., Guo, Y. et al. A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS. Circuits Syst Signal Process 40, 3125–3142 (2021). https://doi.org/10.1007/s00034-020-01643-z

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