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FPGA Implementation of Modified Recursive Box Filter-Based Fast Bilateral Filter for Image Denoising

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Abstract

Bilateral filter (BF) is a type of edge-preserving smoother that is widely utilized in most image processing, computational photography, and computer vision applications. This article presents FPGA implementation of a modified recursive box filter (MRBF)-based fast BF (FBF) architecture for reducing computational complexity, area, and power. In addition, implementation of MRBF uses a modified carry select adder using quantum-dot cellular automata technology that offers lower area, less power consumption, and less delay. Furthermore, as an application, an investigation of image denoising with the proposed MRBF-FBF is also performed. Extensive simulation and hardware results disclose that the proposed FPGA implementation of MRBF-FBF outperforms the conventional filtering techniques in terms of quality assessment of the denoised image, such as peak signal-to-noise ratio and structural similarity index.

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Data Availability

The datasets analyzed during the current study are available in the http://imageprocessingplace.com/root_files_V3/image_databases.htm.

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Authors and Affiliations

  1. Electronics and Communication Engineering, Sathyabama Institute of Science and Technology, Jeppiaar Nagar, Rajiv Gandhi Salai, Chennai, Tamilnadu, India

    Gollamandala Udaykiran Bhargava

  2. Electronics and Communication Engineering, Vidya Jyothi Institute of Technology, Hyderabad, Telangana, India

    Sivakumar Vaazi Gangadharan

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  1. Gollamandala Udaykiran Bhargava
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  2. Sivakumar Vaazi Gangadharan
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Correspondence to Gollamandala Udaykiran Bhargava.

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Bhargava, G.U., Gangadharan, S.V. FPGA Implementation of Modified Recursive Box Filter-Based Fast Bilateral Filter for Image Denoising. Circuits Syst Signal Process 40, 1438–1457 (2021). https://doi.org/10.1007/s00034-020-01538-z

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