Skip to main content
SpringerLink
Log in

A Switched Capacitor-Based SAR ADC Employing a Passive Reference Charge Sharing and Charge Accumulation Technique

  • Published:
Circuits, Systems, and Signal Processing Aims and scope Submit manuscript

Abstract

In this work, a switched capacitor-based successive approximation register (SAR) analog-to-digital converter (ADC) using a passive reference charge sharing and charge accumulation is proposed. For N-bit resolution, the fully differential version of this architecture needs only 6 capacitors, which is a significant improvement over conventional binary-weighted SAR ADC. The proposed SAR ADC is first modeled in MATLAB, and the effect of practical operational transconductance amplifier limitations such as finite values of gain, unity-gain bandwidth and slew rate on ADC characteristics is verified through behavioral simulations. To validate the proposed ADC performance, an 11-bit 2 kS/s SAR ADC is designed and laid out in UMC 180 nm 1P6M CMOS technology with a supply voltage of 1.8 V. The total design occupies an area of \(568\,\upmu \hbox {m} \times 298\,\upmu \hbox {m}\) and consumes a power as less as \(0.28\,\upmu \hbox {W}\). It is found that the integral nonlinearity and differential nonlinearity of this ADC are in the range + 0.35/− 0.84 least significant bit (LSB) and + 0.1/− 0.6 LSB, respectively. In addition, dynamic performance test shows that the proposed SAR ADC offers an effective number of bits of 10.14 and a Walden figure of merit (FoMW) of 0.12 pJ/conv-step.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17

Similar content being viewed by others

References

  1. P.E. Allen, D.R. Holberg, P.E. Allen, P. Allen, CMOS Analog Circuit Design (Holt, Rinehart and Winston, New York, 1987)

    Google Scholar 

  2. H. Aminzadeh, A low-cost tiny-size successive approximation ADC for applications requiring low-resolution conversion with moderate sampling rate. Circuits Syst. Signal Process. 38(1), 242–258 (2019)

    Article  Google Scholar 

  3. S. Asghar, S.S. Afridi, A. Pillai, A. Schuler, M. José, I. O’Connell, A 2-MS/s, 11.22 ENOB, extended input range SAR ADC with improved DNL and offset calculation. IEEE Trans. Circuits Syst. I Regul. Pap. 65(11), 3628–3638 (2018)

    Google Scholar 

  4. S. Babayan-Mashhadi, R. Lotfi, Analysis and design of a low-voltage low-power double-tail comparator. IEEE Trans. Very Large Scale Integr. (VISI) Syst. 22(2), 343–352 (2014)

    Article  Google Scholar 

  5. B. Chen, M. Maddox, M.C. Coln, Y. Lu, L.D. Fernando, Precision passive-charge-sharing SAR ADC: analysis, design, and measurement results. IEEE J. Solid-State Circuit 53(5), 1481–1492 (2018)

    Article  Google Scholar 

  6. C.H. Chen, Y. Zhang, J. Ceballos, G. Temes, Noise-shaping SAR ADC using three capacitors. Electron. Lett. 49(3), 182–184 (2013)

    Article  Google Scholar 

  7. F. Chen, A.P. Chandrakasan, V. Stojanovic, A low-power area-efficient switching scheme for charge-sharing DACs in SAR ADCs, in IEEE Custom Integrated Circuits Conference 2010 (IEEE, 2010), p. 1–4

  8. J. Craninckx, G. Van der Plas, A 65fJ/conversion-step 0-to-50MS/s 0-to-0.7 mW 9b charge-sharing SAR ADC in 90nm digital CMOS, in 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (IEEE, 2007), pp. 246–600

  9. I. Das, M. Sahoo, P. Roy, H. Rahaman, A 45 uW 13 pJ/conv-step 7.4-ENOB 40 kS/s SAR ADC for digital microfluidic biochip applications, in 18th International Symposium on VLSI Design and Test (IEEE, 2014), pp 1–6

  10. Z. Fazel, S. Saeedi, M. Atarodi, Pipelining method for low-power and high-speed SAR ADC design. Analog Integr. Circuits Signal Process. 87(3), 353–368 (2016)

    Article  Google Scholar 

  11. D. Jagadish, Design of low power successive approximation register analog-to-digital converter. PhD thesis, National Institute of Technology Karnataka, India (2017)

  12. P. Jespers, The gm/ID Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits: The Semi-Empirical and Compact Model Approaches (Springer, Berlin, 2009)

  13. C.C. Liu, S.J. Chang, G.Y. Huang, Y.Z. Lin, A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure. IEEE J. Solid-State Circuits 45(4), 731–740 (2010)

    Article  Google Scholar 

  14. S.A. Mahmoud, H.A. Salem, H.M. Albalooshi, An 8-bit, 10 KS/s, \(1.87\,\mu \text{ W }\) successive approximation analog to digital converter in \(0.25\,\mu \text{ m }\) CMOS technology for ECG detection systems. Circuits Syst. Signal Process. 34(8), 2419–2439 (2015)

    Article  Google Scholar 

  15. Y. Mekkattillam, S. Mohapatra, N.R. Mohapatra, Design and calibration of 14-bit 10 KS/s low power SAR ADC for bio-medical applications, in International Symposium on VLSI Design and Test (Springer, 2019), pp. 590–604

  16. B. Murmann, et al. ADC performance survey 1997–2016 (2016). http://www.stanfordedu/murmann/adcsurveyhtml

  17. K. Obata, K. Matsukawa, T. Miki, Y. Tsukamoto, K. Sushihara, A 97.99 dB SNDR, 2 kHz BW, \(37.1\,\mu \text{ W }\) noise-shaping SAR ADC with dynamic element matching and modulation dither effect, in 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) (IEEE, 2016), p. 1–2

  18. S. Pavan, R. Schreier, G.C. Temes, Understanding Delta–Sigma Data Converters (Wiley, New York, 2017)

    Google Scholar 

  19. S. Polineni, A.K. Gupta, 8-bit Nano watt level crossing ADC for bio-medical application, in 2015 International Conference on Computer, Communication and Control (IC4) (IEEE, 2015), pp. 1–6

  20. S. Polineni, M. Bhat, A. Rajan, A 10-Bit differential ultra-low-power SAR ADC with an enhanced MSB capacitor-split switching technique. Arab. J. Sci. Eng. 44(3), 2345–2353 (2019)

    Article  Google Scholar 

  21. P.J. Quinn, A.H. Van Roermund, Switched-Capacitor Techniques for High-Accuracy Filter and ADC Design (Springer, New York, 2007)

    Book  Google Scholar 

  22. T. Rabuske, J. Fernandes, Charge-Sharing SAR ADCs for Low-Voltage Low-Power Applications (Springer, New York, 2017)

    Book  Google Scholar 

  23. B. Razavi, The bootstrapped switch [a circuit for all seasons]. IEEE Solid-State Circuits Magazine 7(3), 12–15 (2015)

    Article  Google Scholar 

  24. R. Schreier, G.C. Temes et al., Understanding Delta–Sigma Data Converters, vol. 74 (IEEE Press, Piscataway, 2005)

    Google Scholar 

  25. P. Sreenivasulu, G.H. Rao, S. Rekha, M. Bhat, A 0.3 V, 56 dB DR, 100 Hz fourth order low-pass filter for ECG acquisition system. Microelectron. J. 94, 104652 (2019)

    Article  Google Scholar 

  26. R.E. Suarez, P.R. Gray, D.A. Hodges, All-MOS charge-redistribution analog-to-digital conversion techniques. II. IEEE J. Solid-State Circuit 10(6), 379–385 (1975)

    Article  Google Scholar 

  27. H.W. Ting, B.D. Liu, S.J. Chang, A histogram-based testing method for estimating A/D converter performance. IEEE Trans. Instrum. Meas. 57(2), 420–427 (2008)

    Article  Google Scholar 

  28. X. Tong, M. Song, Y. Chen, S. Dong, A 10-Bit 120 kS/s SAR ADC without reset energy for biomedical electronics. Circuits Syst. Signal Process. 38(12), 5411–5425 (2019)

    Article  Google Scholar 

  29. R.H. Walden, Analog-to-digital converter survey and analysis. IEEE J. Sel. Areas Commun. 17(4), 539–550 (1999)

    Article  MathSciNet  Google Scholar 

  30. J.G. Webster, Medical Instrumentation: Application and Design (Wiley, New York, 2009)

    Google Scholar 

  31. B. Yazdani, A. Khorami, M. Sharifkhani, Low-power DAC with charge redistribution sampling method for SAR ADCs. Electron. Lett. 52(3), 187–188 (2015)

    Article  Google Scholar 

  32. C. Yuan, Y. Lam, Low-energy and area-efficient tri-level switching scheme for SAR ADC. Electron. Lett. 48(9), 482–483 (2012)

    Article  Google Scholar 

  33. Z. Zheng, U.K. Moon, J. Steensgaard, B. Wang, G.C. Temes, Capacitor mismatch error cancellation technique for a successive approximation A/D converter, in ISCAS’99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No. 99CH36349), vol 2 (IEEE, 1999). pp. 326–329

Download references

Acknowledgements

We would like to thank the MeitY India for funding this research. We would like to express our special thanks to Dr. Ramesh Kini M for CAD support and NITK VLSI research group for the valuable discussions.

Author information

Authors and Affiliations

  1. Department of ECE, National Institute of Technology Karnataka, Surathkal, 575025, India

    Sreenivasulu Polineni, M. S. Bhat & S. Rekha

Authors
  1. Sreenivasulu Polineni
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. M. S. Bhat
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. S. Rekha
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Sreenivasulu Polineni.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Polineni, S., Bhat, M.S. & Rekha, S. A Switched Capacitor-Based SAR ADC Employing a Passive Reference Charge Sharing and Charge Accumulation Technique. Circuits Syst Signal Process 39, 5352–5370 (2020). https://doi.org/10.1007/s00034-020-01437-3

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00034-020-01437-3

Keywords

Search

Navigation