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Hardware-Efficient VLSI Design for Cascade Support Vector Machine with On-Chip Training and Classification Capability

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Abstract

Local processing of machine learning algorithms like support vector machine (SVM) is preferred over the cloud for many real-time embedded applications. However, such embedded systems often have stringent energy constraints besides throughput and accuracy requirements. Hence, hardware-efficient design to compute SVM is critical to enable these applications. In this paper, a hardware-efficient SVM learning unit is proposed using reduced number of multiplications and approximate computing techniques. These design techniques helped the learning unit to achieve 46.97% and 35.72% reductions in area and power when compared with those of the design using full multipliers. The proposed SVM learning unit supports on-chip training and classification. Energy-efficient dual-core, quad-core and octa-core cascade SVM systems were developed using the proposed SVM learning unit to expedite the on-chip training process. The runtime and energy efficiency of the cascade SVM systems improved with an increase in the number of cores. Interestingly, an average speedup of 421x in training time and a remarkable energy reduction of 24,497x were observed for the octa-core cascade SVM system when compared with the software SVM solution running on Intel Core i5-5257U processor. Moreover, the proposed octa-core cascade SVM system showed 73.75% and 65.78% lower area and power, respectively, than those of state-of-the-art cascade SVM architecture.

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References

  1. A. Abdelaziz, M. Elhoseny, A.S. Salama, A. Riad, A machine learning model for improving healthcare services on cloud computing environment. Measurement 119, 117–128 (2018)

    Google Scholar 

  2. S. Afifi, H. GholamHosseini, R. Sinha, Dynamic hardware system for cascade SVM classification of melanoma. Neural Comput. Appl. 32, 1777–1788 (2020)

    Google Scholar 

  3. M.A.B. Altaf, J. Yoo, A \(1.83\mu \text{ J }\)/classification, 8-channel, patient-specific epileptic seizure classification SoC using a non-linear support vector machine. IEEE Trans. Biomedi. Circuits Syst. 10(1), 49–60 (2016)

    Google Scholar 

  4. D. Anguita, A. Boni, S. Ridella, Learning algorithm for nonlinear support vector machines suited for digital VLSI. Electron. Lett. 35(16), 1349–1350 (1999)

    Google Scholar 

  5. D. Anguita, A. Boni, S. Ridella, A digital architecture for support vector machines: theory, algorithm, and FPGA implementation. IEEE Trans. Neural Netw. 14(5), 993–1009 (2003)

    Google Scholar 

  6. D. Anguita, S. Pischiutta, S. Ridella, D. Sterpi, Feed-forward support vector machine without multipliers. IEEE Trans. Neural Netw. 17(5), 1328–1331 (2006)

    Google Scholar 

  7. D. Anguita, S. Ridella, F. Rivieccio, R. Zunino, Hyperparameter design criteria for support vector classifiers. Neurocomputing 55(1–2), 109–134 (2003)

    MATH  Google Scholar 

  8. S. Aziz, M. Dowling, machine learning and AI for risk management. In: Disrupting Finance, pp. 33–50. Springer (2019)

  9. L. Carvalho, A. von Wangenheim, 3D object recognition and classification: a systematic literature review. Pattern Anal. Appl. 22, 1243–1292 (2019)

    MathSciNet  Google Scholar 

  10. S. Chakrabartty, G. Cauwenberghs, Sub-microwatt analog VLSI trainable pattern classifier. IEEE J. Solid State Circuits 42(5), 1169–1179 (2007)

    Google Scholar 

  11. S.K. Chandrinos, G. Sakkas, N.D. Lagaros, AIRMS: a risk management tool using machine learning. Expert Syst. Appl. 105, 34–48 (2018)

    Google Scholar 

  12. C. Cortes, V. Vapnik, Support-vector networks. Mach. Learn. 20(3), 273–297 (1995)

    MATH  Google Scholar 

  13. K. Duan, S.S. Keerthi, A.N. Poo, Evaluation of simple performance measures for tuning SVM hyperparameters. Neurocomputing 51, 41–59 (2003)

    Google Scholar 

  14. S. Esmaeeli, I. Gholampour, Reduced memory requirement in hardware implementation of svm classifiers, in 20th Iranian Conference on Electrical Engineering (ICEE2012), pp. 46–50. IEEE (2012)

  15. A. Esteva, A. Robicquet, B. Ramsundar, V. Kuleshov, M. DePristo, K. Chou, C. Cui, G. Corrado, S. Thrun, J. Dean, A guide to deep learning in healthcare. Nat. Med. 25, 24–29 (2019)

    Google Scholar 

  16. L. Feng, Z. Li, Y. Wang, VLSI design of SVM-based seizure detection system with on-chip learning capability. IEEE Trans. Biomedi. Circuits Syst. 12(1), 171–181 (2018)

    Google Scholar 

  17. R. Genov, G. Cauwenberghs, Kerneltron: support vector “machine” in silicon. IEEE Trans. Neural Netw. 14(5), 1426–1434 (2003)

    MATH  Google Scholar 

  18. H.P. Graf, E. Cosatto, L. Bottou, I. Dourdanovic, V. Vapnik, Parallel support vector machines: The cascade svm, in Advances in neural information processing systems, pp. 521–528 (2005)

  19. T.K. Ho, E.M. Kleinberg, Building projectable classifiers of arbitrary complexity, in it Proceedings of the 13th International Conference on Pattern Recognition (1996)

  20. Intel Open Source Technology Center, PowerTop 2, 9 (2017)

  21. K. Irick, M. DeBole, V. Narayanan, A. Gayasen, A hardware efficient support vector machine architecture for FPGA, in 2008 16th International Symposium on Field-Programmable Custom Computing Machines, pp. 304–305. IEEE (2008)

  22. K. Kang, T. Shibata, An on-chip-trainable Gaussian-kernel analog support vector machine. IEEE Trans. Circuits Sys. I Regul. Pap. 57(7), 1513–1524 (2010)

    MathSciNet  Google Scholar 

  23. F.M. Khan, M.G. Arnold, W.M. Pottenger, Hardware-based support vector machine classification in logarithmic number systems, in 2005 IEEE International Symposium on Circuits and Systems, pp. 5154–5157. IEEE (2005)

  24. A. Krizhevsky, I. Sutskever, G.E. Hinton, Imagenet classification with deep convolutional neural networks, in Advances in Neural Information Processing Systems, pp. 1097–1105 (2012)

  25. T.W. Kuan, J.F. Wang, J.C. Wang, P.C. Lin, G.H. Gu et al., VLSI design of an SVM learning core on sequential minimal optimization algorithm. IEEE Trans. Very Large Scale Integr. Syst. 20(4), 673–683 (2012)

    Google Scholar 

  26. C. Kyrkou, C.S. Bouganis, T. Theocharides, M.M. Polycarpou, Embedded hardware-efficient real-time classification with cascade support vector machines. IEEE Trans. Neural Netw. Learn. Syst. 27(1), 99–112 (2016)

    MathSciNet  Google Scholar 

  27. C. Kyrkou, T. Theocharides, C.S. Bouganis, M. Polycarpou, Boosting the hardware-efficiency of cascade support vector machines for embedded classification applications. Int. J. Parallel Program. 46(6), 1220–1246 (2018)

    Google Scholar 

  28. M. Loukrakpam, M. Choudhury, Error-aware design procedure to implement hardware-efficient antilogarithmic converters. Circuits Syst. Signal Process. 38, 4266–4279 (2019)

    Google Scholar 

  29. M. Loukrakpam, C.L. Singh, M. Choudhury, Energy-efficient approximate squaring hardware for error-resilient digital systems, in 2018 IEEE Electron Devices Kolkata Conference (EDKCON), pp. 202–206. IEEE (2018)

  30. A. L’heureux, K. Grolinger, H.F. Elyamany, M.A. Capretz, Machine learning with big data: challenges and approaches. IEEE Access 5(5), 777–797 (2017)

    Google Scholar 

  31. O.L. Mangasarian, W.N. Street, W.H. Wolberg, Breast cancer diagnosis and prognosis via linear programming. Oper. Res. 43(4), 570–577 (1995)

    MathSciNet  MATH  Google Scholar 

  32. P. Misra, et al.: Machine learning and time series: real world applications, in 2017 International Conference on Computing, Communication and Automation (ICCCA), pp. 389–394. IEEE (2017)

  33. J.N. Mitchell, Computer multiplication and division using binary logarithms. IRE Trans. Electron. Comput. 11(4), 512–517 (1962)

    MathSciNet  MATH  Google Scholar 

  34. V. Mitra, G. Sivaraman, H. Nam, C. Espy-Wilson, E. Saltzman, M. Tiede, Hybrid convolutional neural networks for articulatory and acoustic information based speech recognition. Speech Commun. 89, 103–112 (2017)

    Google Scholar 

  35. A.B. Nassif, I. Shahin, I. Attili, M. Azzeh, K. Shaalan, Speech recognition using deep neural networks: a systematic review. IEEE Access 7, 19143–19165 (2019)

    Google Scholar 

  36. M. Papadonikolakis, C.S. Bouganis, Novel cascade FPGA accelerator for support vector machines classification. IEEE Trans. Neural Netw. Learn. Syst. 23(7), 1040–1052 (2012)

    Google Scholar 

  37. I.C. Passos, P. Ballester, J.V. Pinto, B. Mwangi, F. Kapczinski, Big data and machine learning meet the health sciences, in Personalized Psychiatry, pp. 1–13. Springer (2019)

  38. M. Price, J.R. Glass, A.P. Chandrakasan, A 6 mW, 5,000-word real-time speech recognizer using WFST models. IEEE J. Solid State Circuits 50(1), 102–112 (2015)

    Google Scholar 

  39. J. Qiu, Q. Wu, G. Ding, Y. Xu, S. Feng, A survey of machine learning for big data processing. EURASIP J. Adv. Signal Process. 2016(1), 1–16 (2016)

    Google Scholar 

  40. V. Sze, Designing hardware for machine learning: the important role played by circuit designers. IEEE Solid State Circuits Magaz. 9(4), 46–54 (2017)

    Google Scholar 

  41. V.N. Vapnik, The Nature of Statistical Learning Theory (Springer, New York, 1995)

    MATH  Google Scholar 

  42. Q. Wang, P. Li, Y. Kim, A parallel digital VLSI architecture for integrated support vector machine training and classification. IEEE Trans. Very Large Scale Integr. Syst. 23(8), 1471–1484 (2015)

    Google Scholar 

  43. Y. Wang, Z. Li, L. Feng, H. Bai, C. Wang, Hardware design of multiclass SVM classification for epilepsy and epileptic seizure detection. IET Circuits Dev. Syst. 12(1), 108–115 (2017)

    Google Scholar 

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Manipur Technical University, Imphal, India

    Merin Loukrakpam

  2. Department of Electronics and Communication Engineering, NIT Silchar, Silchar, India

    Merin Loukrakpam & Madhuchhanda Choudhury

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  1. Merin Loukrakpam
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  2. Madhuchhanda Choudhury
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Correspondence to Merin Loukrakpam.

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Loukrakpam, M., Choudhury, M. Hardware-Efficient VLSI Design for Cascade Support Vector Machine with On-Chip Training and Classification Capability. Circuits Syst Signal Process 39, 5272–5297 (2020). https://doi.org/10.1007/s00034-020-01415-9

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