Using the multi-valued logic causes the reduction in interconnections, thereby leading to the reduction in chip area and interconnection power dissipation. In order to take advantage of the multi-valued logic, the structure of a mixed-radix system using multi-valued and binary logic is more suitable than that of only using the multi-valued logic; so, the design of a multi-digit converter is necessary. In this paper, first, a new efficient quaternary-to-binary converter and a binary-to-quaternary converter based on multi-threshold voltage are designed using carbon nanotube field effect transistor (CNTFET). Then, multi-digit quaternary-to-binary and binary-to-quaternary algorithms are discussed and implemented. Subsequently, these converters are used in a multi-digit quaternary adder. It is shown that, if quaternary numbers are initially converted into binary numbers and then summation is performed (by using multi-digit quaternary-to-binary and binary-to-quaternary converters), the complexity is considerably reduced, as compared with using the quaternary full adders. Also, some other applications of these converters are discussed. The simulation results using the Stanford 32-nm CNTFET model in the HSPICE software at 0.9 V indicate the correct operation and the high performance of the proposed designs.
This is a preview of subscription content, access via your institution.
Buy single article
Instant access to the full article PDF.
Tax calculation will be finalised during checkout.
E. Abiri, A. Darabi, S. Salem, Design of multiple-valued logic gates using gate-diffusion input for image processing applications. Comput. Electr. Eng. 69, 142–157 (2018)
P. Avouris, J. Appenzeller, R. Martel, S.J. Wind, Carbon nanotube electronics. Proc. IEEE 91, 1772–1784 (2003)
P.C. Balla, A. Antoniou, Low power dissipation MOS ternary logic family. IEEE J. Solid-State Circuits 19(5), 739–749 (1984)
CNFET Model. http://nano.stanford.edu/models
K.W. Current, Current-mode CMOS multiple-valued logic circuits. IEEE J. Solid-State Circuits 29, 95–107 (1994)
A. Daraei, S.A. Hosseini, Novel energy-efficient and high-noise margin quaternary circuits in nanoelectronics. AEU Int. J. Electron. Commun. 105, 145–162 (2019)
S. Das, S. Bhattacharya, D. Das, Performance evaluation of CNTFET-based logic gates using Verilog-AMS, in Proceedings of National Conference on Electronics, Communication and Signal Processing, pp. 85–88 (2011)
J. Deng, H.S. Wong, A compact SPICE model for carbon nanotube field effect transistors including nonidealities and its application. IEEE Trans. Electron Devices 54, 3186–3194 (2007)
S.A. Ebrahimi, M.R. Reshadinezhad, A. Bohlooli, M. Shahsavari, Efficient CNTFET-based design of quaternary logic gates and arithmetic circuit. Microelectron. J. 53, 156–166 (2016)
D. Etiemble, M. Israel, Comparison of binary and multi valued ICs according to VLSI criteria. Computer 21, 28–42 (1988)
A. Heung, H.T. Mouftah, Depletion/enhancement CMOS for a low power family of three-valued logic circuits. IEEE J. Solid-State Circuit Soc. 20(2), 609–616 (1985)
S.A. Hosseini, S. Etezadi, A novel very low-complexity multi-valued logic comparator in nanoelectronics. Circuits Syst. Signal Process. (2019). https://doi.org/10.1007/s00034-019-01158-2
S.L. Hurst, Multiple-valued logic its status and its future. IEEE Trans. Comput. 33, 1160–1179 (1984)
P. Keshavarzian, R. Sarikhani, A novel CNTFET-based ternary full adder. Circuits Syst. Signal Process. 33, 665–679 (2014)
Y. Lin, J. Appenzeller, J. Knoch, P. Avouris, High-performance carbon nanotube field-effect transistor with tunable polarities. IEEE Trans. Nanotechnol. 4(5), 481–489 (2005)
S. Lin, Y.B. Kim, F. Lombardi, CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE Trans. Nanotechnol. 10(2), 217–225 (2011)
M.S. Mastoori, F. Razaghian, A novel energy-efficient ternary successor and predecessor using CNTFET. Circuits Syst. Signal Process. 35, 875–895 (2016)
P.L. McEuen, M.S. Fuhrer, H. Park, Single-walled carbon nanotube electronics. IEEE Trans. Nanotechnol. 1(1), 78–85 (2002)
M. Mishra, S.H. Akashe, High performance, low power 200 Gb/s 4:1 MUX with TGLin 45 nm technology. Appl. Nanosci. (2014). https://doi.org/10.1007/s13204-013-0206-0
M. Mukaidono, Regular ternary logic functions suitable for treating ambiguity. IEEE Trans. Comput. 35, 179–183 (1986)
K. Rahbari, S.A. Hosseini, Novel ternary D-Flip-Flap-Flop and counter based on successor and predecessor in nanotechnology. AEU Int. J. Electron. Commun. 109, 107–120 (2019)
A. Raychowdhury, K. Roy, Carbon nanotube electronics: design of high-performance and low-power digital circuits. IEEE Trans. Circuits Syst. I, Reg. Pap. 54(11), 2391–2401 (2007)
E. Roosta, S.A. Hosseini, Anovel multiplexer-based quaternary full adder in nanoelectronics. Circuits Syst. Signal Process. (2019). https://doi.org/10.1007/s00034-019-01039-8
M. Shahangian, S.A. Hosseini, S.H. Pishgar Komleh, Design of a multi-digit binary-to-ternary converter based on CNTFETs. Circuit Syst. Signal Process. 38(6), 2544–2563 (2019)
E. Shahrom, S.A. Hosseini, A new low power multiplexer based ternary multiplier using CNTFETs. Int. J. Electron. Commun. 93, 191–207 (2018)
F. Sharifi, M.H. Moaiyeri, K. Navi, A novel quaternary full adder cell based on nanotechnology. Mod. Educ. Comput. Sci. 7(3), 19–25 (2015)
K. Sridharan, S. Gurindagunta, V. Pudi, Efficient multiternary digit adder design in CNTFET technology. IEEE Trans. Nanotechnol. 12(3), 283–287 (2013)
B. Srinivasu, K. Sridharan, Low complexity multiternary digit multiplier design in CNTFET technology. IEEE Trans. 63, 753–757 (2016)
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
About this article
Cite this article
Ghelichkhan, M., Hosseini, S.A. & Pishgar Komleh, S.H. Multi-digit Binary-to-Quaternary and Quaternary-to-Binary Converters and Their Applications in Nanoelectronics. Circuits Syst Signal Process 39, 1920–1942 (2020). https://doi.org/10.1007/s00034-019-01235-6
- Multi-digit adder
- Multi-digit binary-to-quaternary converter
- Quaternary-to-binary converter