An Improved Low-Power Coding for Serial Network-On-Chip Links


In the fast nanosilicon revolution era, network-on-chip (NoC) architecture offers a significant research solution to on-chip multiprocessor-based real-time applications. As the number of cores increases, power consumption of the resources of NoC also increases. Links are the major power dissipator in NoC architecture owing to switching activity of data bits communicated through them. The performance of data communication links in NoC is strongly dependent on the factor of power dissipation. An efficient coding method is needed to reduce both coupling and self-switching activity of data bits of NoC links. In this work, an improved low-power encoding algorithm for serial links is proposed to reduce switching transition for any random data pattern making them more suited to real-time applications. The proposed encoding algorithm is coded, simulated and verified its area and power performance using Synopsys tools utilizing UMC 90 nm technology. Experimental results have shown that it provides on average 48.83% of switching activity reduction for any real-time applications.

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Correspondence to Sivakumar Rajagopal.

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Velayudham, S., Rajagopal, S. & Ko, SB. An Improved Low-Power Coding for Serial Network-On-Chip Links. Circuits Syst Signal Process 39, 1896–1919 (2020).

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  • Network-on-chip
  • Serial links
  • Transmission coding
  • Switching activity reduction