An Improved Low-Power Coding for Serial Network-On-Chip Links

Abstract

In the fast nanosilicon revolution era, network-on-chip (NoC) architecture offers a significant research solution to on-chip multiprocessor-based real-time applications. As the number of cores increases, power consumption of the resources of NoC also increases. Links are the major power dissipator in NoC architecture owing to switching activity of data bits communicated through them. The performance of data communication links in NoC is strongly dependent on the factor of power dissipation. An efficient coding method is needed to reduce both coupling and self-switching activity of data bits of NoC links. In this work, an improved low-power encoding algorithm for serial links is proposed to reduce switching transition for any random data pattern making them more suited to real-time applications. The proposed encoding algorithm is coded, simulated and verified its area and power performance using Synopsys tools utilizing UMC 90 nm technology. Experimental results have shown that it provides on average 48.83% of switching activity reduction for any real-time applications.

This is a preview of subscription content, access via your institution.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8

References

  1. 1.

    M. Ali, M.N. Islam, A.B.M. Foysal, Algorithms for generating binary reflected gray code sequence: time efficient approaches. in International Conference on Future Computer and Communication, pp. 79–83 (2009)

  2. 2.

    S. Bae, Big-O Notation. in: JavaScript Data Structures and Algorithms. Apress, Berkeley, CA (2019)

  3. 3.

    L. Benini, G. De Micheli, Networks on chip: a new paradigm for systems on chip design, in Proceedings of Design Automation and Test in Europe Conference and Exhibition, pp. 418–419 (2002)

  4. 4.

    A.R. Bharghava, M.B. Srinivas, Transition inversion based low power data coding scheme for synchronous serial communication. in IEEE Computer Society Annual Symposium on VLSI, pp. 103–108 (2009)

  5. 5.

    S.M. Bhat, D.Y. Jahnavi, Universal rotate invert bus encoding for low power VLSI. Int. J. VLSI Des. Commun. Syst. 3(4), 97–106 (2012)

    Article  Google Scholar 

  6. 6.

    Y. Chen, T. Krishna, J.S. Emer, V. Sze, Eyeriss: an energy-efficient reconfigurable accelerator for deep convolutional neural networks. IEEE J. Solid-State Circuits 52(1), 127–138 (2017)

    Article  Google Scholar 

  7. 7.

    C. Chiu, W. Huang, C. Lin, W. Lai, Y. Tsao, Embedded transition inversion coding with low switching activity for serial links. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 21(10), 1797–1810 (2013)

    Article  Google Scholar 

  8. 8.

    W.J. Dally, B. Towles, Route packets, not wires: on-chip interconnection networks, in Proceedings of Design Automation Conference, pp. 684–689 (2001)

  9. 9.

    D. DiTomaso, A. Sikder, A. Kodi, A. Louri, Machine learning enabled power-aware network-on-chip design. in Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1354–1359 (2017)

  10. 10.

    R.R. Dobkin, A. Morgenshtein, A. Kolodny , R. Ginosar, Parallel vs. serial on-chip communication. in Proceedings of the 2008 International Workshop on System Level Interconnect Prediction, pp. 43–50 (2008)

  11. 11.

    A. Firuzan, M. Modarressi, M. Daneshtalab, M. Reshadi, Reconfigurable network-on-chip for 3D neural network accelerators. in Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Turin, pp. 1–8 (2018)

  12. 12.

    F. Gebali, H. Elmiligi, M.W. El-Kharashi, Networks-on-Chips; Theory and Practice (Taylor & Francis, New York, 2011)

    MATH  Google Scholar 

  13. 13.

    M. Ghoneima, Y. Ismail, M. Khellah, V. De, Reducing the data switching activity on serial link buses. in 7th International Symposium on Quality Electronic Design (ISQED’06), San Jose, CA, pp. 427–432 (2006)

  14. 14.

    M. Ghoneima, Y.I. Ismail, M.M. Khellah, J.W. Tschanz, V. De, Formal derivation of optimal active shielding for low-power on-chip buses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5), 821–836 (2006)

    Article  Google Scholar 

  15. 15.

    M. Ghoneima, Y. Ismail, M.M. Khellah, J. Tschanz, V. De, Serial-link bus: a low-power on-chip bus architectured. IEEE Trans. Circuits Syst. I Regul. Pap. 56(9), 2020–2032 (2009)

    MathSciNet  Article  Google Scholar 

  16. 16.

    S. Ghosh, P. Ghosal, N. Das, S.P. Mohanty, O. Okobiah, Data correlation aware serial encoding for low switching power on-chip communication. in Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 124–129 (2014)

  17. 17.

    H. Guo, Shifted Gray encoding to reduce instruction memory address bus switching for low-power embedded systems. Austr. J. Syst. Arch. 56, 180–190 (2010)

    Article  Google Scholar 

  18. 18.

    A. Hemani et al., Network on chip: an architecture for billion transistor era, in Proceedings of IEEE NorChip, pp. 1–8 (2000)

  19. 19.

    S. Hong, U. Narayanan, K.-S. Chung, T. Kim, Bus-invert coding for Low power I/O decomposition approach. in Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems, vol. 2, pp. 750–753 (2000)

  20. 20.

    N. Jafarzadeh, M. Palesi, A. Khademzadeh, A. Afzali-Kusha, Data encoding techniques for reducing energy consumption in network-on-chip. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(3), 675–685 (2014)

    Article  Google Scholar 

  21. 21.

    D. Jahier Pagliari, E. Macii, M. Poncino, Zero-transition serial encoding for image sensors. IEEE Sens. J. 17(8), 2563–2571 (2017)

    Article  Google Scholar 

  22. 22.

    L. Kangmin, S.-J. Lee, H.-J. Yoo, SILENT: serialized low energy transmission coding for on-chip interconnection networks. in IEEE/ACM International Conference on Computer Aided Design, pp. 448–451 (2004)

  23. 23.

    Z. Khan, T. Arslan, A.T. Erdogan, Low power system on chip bus encoding scheme with crosstalk noise reduction capability. IEE Proc. Comput. Digit. Tech. 153, 101–108 (2006)

    Article  Google Scholar 

  24. 24.

    K.-W. Kim, K.-H. Baek, N. Shanbhag, C.L. Liu, S.-M. Kang, Coupling-driven signal encoding scheme for low-power interface design. in IEEE/ACM International Conference on Computer Aided Design, pp. 318–321 (2000)

  25. 25.

    S. Kumar et al., A network on chip architecture and design methodology, in Proceedings of IEEE Computer Society Annual Symposium on VLSI, (ISVLSI 2002) Pittsburgh, PA, USA, pp. 105–112 (2002)

  26. 26.

    K. Lee et al., Low-power network-on-chip for high-performance SoC design. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 14(3), 148–160 (2006)

    Google Scholar 

  27. 27.

    H. Li, J. Wang, L. Wu, H. Lam, Y. Gao, Optimal guaranteed cost sliding-mode control of interval type-2 fuzzy time-delay systems. IEEE Trans. Fuzzy Syst. 26(1), 246–257 (2018)

    Article  Google Scholar 

  28. 28.

    W. Ligang, Y. Gao, J. Liu, H. Li, Event-triggered sliding mode control of stochastic systems via output feedback. Automatica 82, 79–92 (2017)

    MathSciNet  Article  Google Scholar 

  29. 29.

    A. Morgenshtein, I. Cidon, A. Kolodny, R. Ginosar, Comparative analysis of serial vs parallel links in NoC. in Proceedings of International Symposium on System-on-Chip, pp. 185–188 (2004)

  30. 30.

    J. Natesan, D. Radhakrishnan, Shift invert coding (SINV) for low power VLSI. in Euromicro Symposium on Digital System Design, pp. 190–194 (2004)

  31. 31.

    D.J. Pagliari, E. Macii, M. Poncino, Approximate energy-efficient encoding for serial interfaces. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 22(4), 1–25 (2017)

    Article  Google Scholar 

  32. 32.

    M. Palesi, F. Fazzino, G. Ascia, V. Catania, Data encoding for low-power in wormhole-switched networks-on-chip. in 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, pp. 119–126 (2009)

  33. 33.

    M. Palesi, G. Ascia, F. Fazzino, V. Catania, Data encoding schemes in networks on chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(5), 774–786 (2011)

    Article  Google Scholar 

  34. 34.

    S. Pasricha, N. Dutt, On-chip Communication Architectures: System on Chip Interconnect (Morgan Kaufmann, Burlington, 2008)

    Google Scholar 

  35. 35.

    A. Ramachandran, B. Rajaram, S. Purini, G. Regeti, Transition inversion based low power data coding scheme for buffered data transfer. in 23rd IEEE International conference on VLSI Design, pp. 164–169 (2010)

  36. 36.

    X. Ren, D. Gao, X. Fan, J. An, Adaptive low-power transmission coding for serial links in network-on-chip. Procedia Eng. 29, 1618–1624 (2012)

    Article  Google Scholar 

  37. 37.

    K.S. Sainarayanan, J.V.R. Ravindra, M.B. Srinivas, A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects. in IEEE International Symposium on Circuits and Systems, pp. 4155–4158 (2006)

  38. 38.

    S. Saponara, L. Fanucci, E. Petri, A multi-processor NoC-based architecture for real-time image/video enhancement. J. Real-Time Image Proc. 8(1), 111–125 (2013)

    Article  Google Scholar 

  39. 39.

    D.N. Sarma, G. Lakshminarayanan, Encoding technique for reducing power dissipation in network on chip serial links. in International Conference on Computational Intelligence and Communication Networks, Gwalior, pp. 323–327 (2011)

  40. 40.

    M.R. Stan, W.P. Burleson, Limited weight codes for low-power I/O. in Proceedings of International Workshop Low-Power Design, pp. 209–214 (1994)

  41. 41.

    M.R. Stan et al., Bus-invert coding for Low-power I/O. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 3(1), 49–58 (1995)

    Article  Google Scholar 

  42. 42.

    A. Stillmaker, B. Baas, Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7nm. Integr. VLSI J. 58, 74–81 (2017)

    Article  Google Scholar 

  43. 43.

    T.M. Supon, I.I. Basith, E. Abdel-Raheem, R. Rashidzadeh, Efficient integrated bus coding scheme for low-power I/O. AEU Int. J. Electron. Commun. 82, 30–36 (2017)

    Article  Google Scholar 

  44. 44.

    M. Taassori, M. Taassori, S. Uysal, MFLP: a low power encoding for on chip networks. Des. Autom. Embedded Syst. 20(3), 191–210 (2016)

    Article  Google Scholar 

  45. 45.

    C.D. Thompson, The VLSI complexity of sorting. IEEE Trans. Comput. C–32(12), 1171–1184 (1983)

    MathSciNet  Article  Google Scholar 

  46. 46.

    J. Yang, R. Gupta, C. Zhang, Frequent value encoding for low power data buses. ACM Trans. Des. Autom. Electron. Syst. 9(3), 354–384 (2004)

    Article  Google Scholar 

  47. 47.

    S. Youngsoo, C. Soo-Ik, C. Kiyoung, Partial bus-invert coding for power optimization of application-specific systems. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 9(2), 377–383 (2001)

    Article  Google Scholar 

  48. 48.

    J. Zeng, J.-Y. Zhou, R.-B. Lin, Transition inversion coding with parity check for offchip serial transmission. in Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 634–637 (2014)

  49. 49.

    M. Zhang, Z. Gan, J. Zhang, Z. Gu, Joint hybrid frequent value cache and multi-coding for data bus energy saving. in 22nd IEEE International Conference on Parallel and Distributed Systems, pp. 869–876 (2016)

Download references

Author information

Affiliations

Authors

Corresponding author

Correspondence to Sivakumar Rajagopal.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Velayudham, S., Rajagopal, S. & Ko, SB. An Improved Low-Power Coding for Serial Network-On-Chip Links. Circuits Syst Signal Process 39, 1896–1919 (2020). https://doi.org/10.1007/s00034-019-01231-w

Download citation

Keywords

  • Network-on-chip
  • Serial links
  • Transmission coding
  • Switching activity reduction