A 7-GHz Fast-Lock Two-Step Time-to-Digital Converter-Based All-Digital DLL


This paper presents a new fast-lock all-digital delay-locked loop (DLL) for next-generation memory devices such as DDR5 SDRAMs. The proposed DLL utilizes a new two-step time-to-digital converter (TDC)-based phase detecting and tracking scheme that results in a fast lock time of less than seven clock cycles. Unlike previous TDC-based DLLs, there is an advantage of having a fast lock time regardless of the long-replica clock buffer delay in the DRAM DLL. Implemented in a 65 nm CMOS process, the proposed digital DLL has a wide operating frequency range of 1.65–7.0 GHz and occupies an area of only 0.021 mm2. The DLL dissipates only 7.1 mW from a 1.0 V supply at 7 GHz, and the effective peak-to-peak (p–p) jitter of the output clock is about 4.55 ps at 7 GHz.

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This research was funded and conducted under “the Competency Development Program for Industry Specialists” of the Korean Ministry of Trade, Industry and Energy (MOTIE), operated by Korea Institute for Advancement of Technology (KIAT). (No. N0001883, HRD Program for N0001883). This work was also supported by National Research Foundation of Korea (NRF 2019R1A2C-1010017). The EDA tools were supported by IDEC.

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Correspondence to Jongsun Kim.

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Park, D., Kim, J. A 7-GHz Fast-Lock Two-Step Time-to-Digital Converter-Based All-Digital DLL. Circuits Syst Signal Process 39, 1715–1734 (2020). https://doi.org/10.1007/s00034-019-01230-x

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  • DDR4
  • DDR5
  • Delay-locked loop
  • DLL
  • Memory