This paper presents a new fast-lock all-digital delay-locked loop (DLL) for next-generation memory devices such as DDR5 SDRAMs. The proposed DLL utilizes a new two-step time-to-digital converter (TDC)-based phase detecting and tracking scheme that results in a fast lock time of less than seven clock cycles. Unlike previous TDC-based DLLs, there is an advantage of having a fast lock time regardless of the long-replica clock buffer delay in the DRAM DLL. Implemented in a 65 nm CMOS process, the proposed digital DLL has a wide operating frequency range of 1.65–7.0 GHz and occupies an area of only 0.021 mm2. The DLL dissipates only 7.1 mW from a 1.0 V supply at 7 GHz, and the effective peak-to-peak (p–p) jitter of the output clock is about 4.55 ps at 7 GHz.
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E. Bayram, A.F. Aref, M. Saeed, R. Negra, 1.5–3.3 GHz, 0.0077 mm2, 7 mW all-digital delay-locked loop with dead-zone free phase detector in 0.13 um CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 65(1), 39–50 (2018)
P. Dudek, S. Szczepanski, J.V. Hatfield, A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line. IEEE J. Solid State Circuits 35(2), 240–247 (2000)
M. Gholami, A novel low power architecture for DLL-based frequency synthesizers. Circuits Syst. Signal Process. 32(2), 781–801 (2013)
M. Hossain, F. Aquil, P.S. Chau, B. Tsang, P. Le, J. Wei, T. Stone, B. Daly, C. Tran, J.C. Eble, K. Knorpp, J.L. Zerbe, A fast-lock, jitter filtering all-digital DLL based burst-mode memory interface. IEEE J. Solid State Circuits 49(4), 1048–1062 (2014)
M. Hsieh, L. Chen, S. Liu, C.C. Chen, A 6.7 MHz to 1.24 GHz 0.0318 mm2 fast-locking all-digital DLL using phase-tracing delay unit in 90 nm CMOS. IEEE J. Solid State Circuits 51(2), 412–427 (2016)
D. Jung, Y. An, K. Ryu, J. Park, S. Jung, All-digital fast-locking delay-locked loop using a cyclic-locking loop for DRAM. IEEE Trans. Circuits Syst II: Express Br. 62(11), 1023–1027 (2015)
J. Kim, S. Han, A high-resolution dual-loop digital DLL. J. Semicond. Technol. Sci. 16(4), 520–527 (2016)
J. Kim, An all-digital delay-locked loop using a lock-in pre-search algorithm. J. Semicond. Technol. Sci. 17(6), 825–831 (2017)
J. Kim, An anti-boundary switching fine-resolution digital delay-locked loop. Analog Integr. Circuits Signal Process. 96(3), 445–454 (2018)
M. Kim, L. Kim, 100 MHz-to-1 GHz open-loop ADDLL with fast lock-time for mobile applications, in IEEE Custom Integrated Circuits Conference, pp. 1–4 (2008)
H. Lee, K. Kim, Y. Choi, J. Sohn, N. Park, K. Kim, C. Kim, Y. Choi, B. Chung, A 1.6 V 1.4 Gbp/s/pin consumer DRAM with self-dynamic voltage scaling technique in 44 nm CMOS technology. IEEE J. Solid State Circuits 47(1), 131–140 (2012)
D. Lee, J. Kim, 5 GHz all-digital delay-locked loop for future memory systems beyond double data rate 4 synchronous dynamic random access memory. Electon. Lett. 51(24), 1973–1975 (2015)
J. Lim, J. Bae, J. Jang, H. Jung, H. Lee, Y. Kim, B. Kim, J. Sim, H. Park, A delay locked loop with a feedback edge combiner of duty-cycle corrector with a 20–80% input duty cycle for SDRAMs. IEEE Trans. Circuits Syst. II: Express Br. 63(2), 141–145 (2016)
D. Park, J. Kim, A 7-GHz fast-lock 2-step TDC-based all-digital DLL for post-DDR4 SDRAMs, in IEEE International Symposium on Circuits and Systems Conference, pp. 1–4 (2018)
D. Park, G. Park, J. Kim, A 0.15 to 2.2 GHz all-digital delay-locked loop, in IEEE International New Circuits and Systems Conference, pp. 261–264 (2017)
D. Shin, J. Song, H. Chae, C. Kim, A 7 ps jitter 0.053 mm2 fast lock all-digital DLL with a wide range and high resolution DCC. IEEE J. Solid State Circuits 44(9), 2437–2451 (2009)
K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K. Lee, J. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D. Jung, B. Kim, J. Choi, S. Jang, C. Kim, J. Lee, J.S. Choi, A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme. IEEE J. Solid State Circuits 48(1), 168–177 (2013)
J. Wang, C. Cheng, An all-digital delay-locked loop using an in-time phase maintenance scheme for low-jitter gigahertz operation. IEEE Trans. Circuits Syst. I Regul. Pap. 62(2), 395–404 (2015)
W. Yun, I. Song, H. Jeoung, H. Choi, S. Lee, J. Kim, C. Kim, J. Choi, S. Jang, J.S. Choi, A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67 Gb/s/pin 16 Gb 4-H stack DDR4 SDRAM with TSVs, in IEEE International Solid-State Circuits Conference, pp. 322–323 (2015)
D. Zhang, H. Yang, W. Zhu, W. Li, Z. Huang, L. Li, T. Li, A multiphase DLL with a novel fast-locking fine-code time-to-digital converter. IEEE Trans. Very Large Scale Integr. (VLSI) Syst 23(11), 2680–2684 (2015)
This research was funded and conducted under “the Competency Development Program for Industry Specialists” of the Korean Ministry of Trade, Industry and Energy (MOTIE), operated by Korea Institute for Advancement of Technology (KIAT). (No. N0001883, HRD Program for N0001883). This work was also supported by National Research Foundation of Korea (NRF 2019R1A2C-1010017). The EDA tools were supported by IDEC.
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Park, D., Kim, J. A 7-GHz Fast-Lock Two-Step Time-to-Digital Converter-Based All-Digital DLL. Circuits Syst Signal Process 39, 1715–1734 (2020). https://doi.org/10.1007/s00034-019-01230-x
- Delay-locked loop