Skip to main content
SpringerLink
Log in

Error-Aware Design Procedure to Implement Hardware-Efficient Antilogarithmic Converters

  • Published:
Circuits, Systems, and Signal Processing Aims and scope Submit manuscript

Abstract

An error-aware design procedure to implement hardware-efficient antilogarithmic converters is proposed in this paper. The procedure is based on a piecewise linear approximation method that estimates the minimum number of segments required to meet a desired error constraint. Hardware designs for 2-, 4-, and 8-segment antilogarithmic converters were implemented using the proposed design procedure. The designs were synthesized in TSMC 65-nm CMOS technology. The synthesis results revealed that the proposed designs exhibited significant energy reductions when compared with state-of-the-art antilogarithmic converters. In terms of error–area–delay–power product, the proposed designs showed improved hardware efficiency over prior antilogarithmic converters of comparable approximation errors.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8

Similar content being viewed by others

References

  1. K.H. Abed, R.E. Siferd, Vlsi implementation of a low-power antilogarithmic converter. IEEE Trans. Comput. 52(9), 1221–1228 (2003)

    Article  Google Scholar 

  2. M.G. Arnold, S. Collange, A real/complex logarithmic number system alu. IEEE Trans. Comput. 60(2), 202–213 (2011)

    Article  MathSciNet  MATH  Google Scholar 

  3. C. Brokish, M. Lewis, in A-Law and \(\mu \) -Law Companding Implementations Using the TMS320C54x (Texas Instruments, SPRA163, 1997)

  4. D. De Caro, N. Petra, A.G. Strollo, Efficient logarithmic converters for digital signal processing applications. IEEE Trans. Circuits Syst. II 58(10), 667–671 (2011)

    Article  Google Scholar 

  5. R. Gutierrez, J. Valls, Low cost hardware implementation of logarithm approximation. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 19(12), 2326–2330 (2011)

    Article  Google Scholar 

  6. M. Ha, S. Lee, Accurate hardware-efficient logarithm circuit. IEEE Trans. Circuits Syst. II 64(8), 967–971 (2017)

    Article  Google Scholar 

  7. E.L. Hall, D.D. Lynch, S. Dwyer, Generation of products and quotients using approximate binary logarithms for digital filtering applications. IEEE Trans. Comput. 100(2), 97–105 (1970)

    Article  MATH  Google Scholar 

  8. K. Johansson, O. Gustafsson, L. Wanhammar, Implementation of elementary functions for logarithmic number systems. IET Comput. Digit. Tech. 2(4), 295–304 (2008)

    Article  Google Scholar 

  9. F. M. Khan, M.G. Arnold, W. M. Pottenger, Hardware-based support vector machine classification in logarithmic number systems, in IEEE International Symposium on Circuits and Systems, 2005. ISCAS 2005. IEEE (2005), pp. 5154–5157

  10. H. Kim, B.G. Nam, J.H. Sohn, J.H. Woo, H.J. Yoo, A 231-mhz, 2.18-mw 32-bit logarithmic arithmetic unit for fixed-point 3-d graphics system. IEEE J. Solid-State Circuits 41(11), 2373–2381 (2006)

    Article  Google Scholar 

  11. H. Kim, B.G. Nam, J.H. Sohn, J.H. Woo, H.J. Yoo, A 231-mhz, 2.18-mw 32-bit logarithmic arithmetic unit for fixed-point 3-d graphics system. IEEE Trans. Solid State Circuits 41(11), 2373–2381 (2006)

    Article  Google Scholar 

  12. C.T. Kuo, T.B. Juang, Area-efficient and highly accurate antilogarithmic converters with multiple regions of constant compensation schemes. Microsyst. Technol. 24(1), 219–225 (2018)

    Article  Google Scholar 

  13. T.C. Lin, S.K. Chen, C.W. Liu. A low-error and rom-free logarithmic arithmetic unit for embedded 3d graphics applications, in 2013 International Symposium on VLSI Design, Automation, and Test (VLSI-DAT). IEEE (2013), pp. 1–4

  14. C.W. Liu, S.H. Ou, K.C. Chang, T.C. Lin, S.K. Chen, A low-error, cost-efficient design procedure for evaluating logarithms to be used in a logarithmic arithmetic processor. IEEE Trans. Comput. 65(4), 1158–1164 (2016)

    Article  MathSciNet  MATH  Google Scholar 

  15. J.N. Mitchell, Computer multiplication and division using binary logarithms. IRE Trans. Electron. Comput. 4, 512–517 (1962)

    Article  MathSciNet  MATH  Google Scholar 

  16. B.G. Nam, H. Kim, H.J. Yoo, Power and area-efficient unified computation of vector and elementary functions for handheld 3d graphics systems. IEEE Trans. Comput. 57(4), 490–504 (2008)

    Article  MathSciNet  MATH  Google Scholar 

  17. S. Paul, N. Jayakumar, S.P. Khatri, A fast hardware approach for approximate, efficient logarithm and antilogarithm computations. IEEE Trans. Very Large Scale Integr. (VLSI) 17(2), 269–277 (2009)

    Article  Google Scholar 

  18. J.A. Pineiro, M.D. Ercegovac, J.D. Bruguera, Algorithm and architecture for logarithm, exponential, and powering computation. IEEE Trans. Comput. 53(9), 1085–1096 (2004)

    Article  Google Scholar 

  19. D. Van Ess, in Algorithm-Logarithmic Signal Companding-not Just a Good idea-it is \(\mu \)-Law. Cypress Semiconductor, AN2095. (2012)

  20. M. Zhu, J. Xiao, W. Wanggen, H. Yajun. Error flatten logarithm approximation for graphics processing unit, in 2011 International Conference on Microelectronics (ICM). IEEE (2011), pp. 1–6

Download references

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, NIT, Silchar, India

    Merin Loukrakpam & Madhuchhanda Choudhury

Authors
  1. Merin Loukrakpam
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Madhuchhanda Choudhury
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Merin Loukrakpam.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Loukrakpam, M., Choudhury, M. Error-Aware Design Procedure to Implement Hardware-Efficient Antilogarithmic Converters. Circuits Syst Signal Process 38, 4266–4279 (2019). https://doi.org/10.1007/s00034-019-01062-9

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00034-019-01062-9

Keywords

Search

Navigation