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High-Throughput, Area-Efficient Architecture of 2-D Block FIR Filter Using Distributed Arithmetic Algorithm

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Abstract

This paper proposes a new architecture of 2-D block FIR filter using distributed arithmetic (DA) algorithm, which is known for the efficient design of multiply and accumulate block. Hardware-based architecture is proposed for DA lookup table (DA-LUT) that makes the architecture of 2-D FIR filter reconfigurable. Further, due to block processing, sharing takes place among DA-LUTs at various stages. Thus, a common DA-LUT may be designed for block inputs which reduce the hardware complexity for DA-LUT. Furthermore, memory overlapping is used to reduce the systolic architectures in proposed design over existing designs. For higher-order 2-D FIR filter, the complexity of DA-LUT is reduced by dividing the internal block into parallel and small blocks. With the help of ASIC synthesis results, a comparative analysis of proposed design with the earlier reported designs is presented, and it is shown that the proposed design leads to significant improvements in various performance parameters.

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Acknowledgements

The authors would like to acknowledge the editor and anonymous reviewers for their significant contributions in the form of valuable suggestions and critics that enriched the content of this manuscript.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, MNNIT, Allahabad, 211004, India

    Prashant Kumar, Prabhat Chandra Shrivastava & Manish Tiwari

  2. Amity University (Lucknow Campus), Lucknow, India

    Ganga Ram Mishra

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  1. Prashant Kumar
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  2. Prabhat Chandra Shrivastava
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  3. Manish Tiwari
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  4. Ganga Ram Mishra
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Correspondence to Prashant Kumar.

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Kumar, P., Shrivastava, P.C., Tiwari, M. et al. High-Throughput, Area-Efficient Architecture of 2-D Block FIR Filter Using Distributed Arithmetic Algorithm. Circuits Syst Signal Process 38, 1099–1113 (2019). https://doi.org/10.1007/s00034-018-0897-2

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  • DOI: https://doi.org/10.1007/s00034-018-0897-2

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