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Reliable VLSI Architecture Design Using Modulo-Quad-Transistor Redundancy Method

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Abstract

In this paper, we propose a new static fault-tolerant technique, viz. modulo-quad-transistor, combining redundancy at circuit level with that at functional level, which offers considerably lower failure rate over all the popular fault-tolerant methods. The new approach of compound redundancy also combines the benefits of the two, reducing the overall performance problems by decreasing area, delay and power overheads. The method is free from the complex interconnection problems of the newly proposed quadded logic with quadded transistor method and also offers higher reliability than it. Low design cost and high reliability of the proposed method have made it suitable for designing fault-tolerant systems for many critical practical applications. Extensive simulation results using some of the ISCAS 85 benchmark circuits along with the detailed theoretical analysis have also been provided to demonstrate the superiority of the proposed method.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, National Institute of Technology Rourkela, Rourkela, India

    Atin Mukherjee

  2. Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur, India

    Anindya Sundar Dhar

Authors
  1. Atin Mukherjee
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  2. Anindya Sundar Dhar
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Correspondence to Atin Mukherjee.

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Mukherjee, A., Dhar, A.S. Reliable VLSI Architecture Design Using Modulo-Quad-Transistor Redundancy Method. Circuits Syst Signal Process 37, 5595–5615 (2018). https://doi.org/10.1007/s00034-018-0837-1

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  • DOI: https://doi.org/10.1007/s00034-018-0837-1

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