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CORDIC-Based High Throughput Sliding DFT Architecture with Reduced Error-Accumulation

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Abstract

This paper presents a COordinate Rotation DIgital Computer (CORDIC)-based architecture of the sliding discrete Fourier transform (SDFT) for the real-time spectrum analysis with a refreshing mechanism through which the design can provide reduced and bounded error-accumulation due to the recursive nature of the existing SDFT algorithms. The proposed design is scalable with the transform length and the calculable number of the DFT bins, and can provide high throughput for a single bin evaluation. The paper also presents the comparison of the conventional and the modulated SDFT architectures based on CORDIC algorithm in terms of the angle-approximation and the truncation errors. The proposed design is synthesized on the Xilinx Virtex-6 FPGA platform and is implemented in ASIC using 90 nm standard cell library.

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Authors and Affiliations

  1. Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur, West Bengal, 721302, India

    Tanmai Kulshreshtha & Anindya Sundar Dhar

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  1. Tanmai Kulshreshtha
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  2. Anindya Sundar Dhar
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Correspondence to Tanmai Kulshreshtha.

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Kulshreshtha, T., Dhar, A.S. CORDIC-Based High Throughput Sliding DFT Architecture with Reduced Error-Accumulation. Circuits Syst Signal Process 37, 5101–5126 (2018). https://doi.org/10.1007/s00034-018-0810-z

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  • DOI: https://doi.org/10.1007/s00034-018-0810-z

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