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Circuits, Systems, and Signal Processing

, Volume 37, Issue 11, pp 4880–4906 | Cite as

Versatile Quaternion Multipliers Based on Distributed Arithmetic

  • Marek Parfieniuk
  • Sang Yoon Park
Article
  • 81 Downloads

Abstract

This paper introduces the idea of versatile circuits for multiplying 4-dimensional hypercomplex numbers in hardware. Depending on the settings of such a device, a variable quaternion can be left- or right-multiplied by a constant coefficient or by its conjugate, as various operations are useful in transform-type algorithms. Multiplierless circuits based on distributed arithmetic (DA) are reviewed that compute quaternion products by additions and bit shifts. It is shown that they can be made versatile by extending memory of partial results, but a better solution is our method for preprocessing bits used to address this memory. The method allows for using the same partial results to compute different inner products that are related to a quaternion multiplication. So versatile multipliers can be implemented with memory optimized so as to save area or to speed up reprogramming compared to the basic DA-based circuit. This has been demonstrated by hardware design experiments, which show that 13–69% area can be saved in a case of ASIC implementation, while for FPGA implementation, spending only 11% more logic resources allows a multiplier to be reprogrammed 75% faster. Additionally, it has been explained how versatile multipliers can be used to realize low-area analysis/synthesis filter banks.

Keywords

Quaternion Hypercomplex Multiplier Distributed arithmetic FPGA Circuit 

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Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of Digital Media and Computer GraphicsBialystok University of TechnologyBialystokPoland
  2. 2.Department of Electronic EngineeringMyongji UniversityYonginKorea

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