A Fast FPGA-Based BCD Adder

Abstract

The binary-coded decimal (BCD) being the more accurate and human-readable representation with ease of conversion is prevailing in the computing and electronic communication. In this paper, a tree-structured parallel BCD addition algorithm is proposed with the reduced time complexity \(O(N(\log _2b)+(N-1))\), where N = number of digits and b = number of bits in a digit. BCD adder is more effective with a lookup table (LUT)-based design, due to field programmable gate array (FPGA) technology’s enumerable benefits and applications. A size-minimal and depth-minimal LUT-based BCD adder circuit construction is the main contribution of this paper. The proposed parallel BCD adder gains a radical achievement compared to the existing best known LUT-based BCD adders. The proposed BCD adder is coded in VHDL and implemented in a Virtex-6 platform targeting XC6VLX75T Xilinx FPGA with a \(-3\) speed grade by using ISE 13.1. The proposed BCD adder provides prominent better performance with 20.0% reduction in area and 41.32% reduction in delay for the post-layout simulation. Since the proposed circuit is improved in both area and delay parameter, it is 53.06% efficient in terms of area-delay product compared to the best known existing BCD adder, which is surely a significant achievement. Moreover, the proposed design consumes 34.28% less power in comparison with existing best known approach at a clock frequency of 200 MHz and a reference voltage of 5 V.

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Correspondence to Hafiz Md. Hasan Babu.

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Ul Haque, M., Sworna, Z.T., Hasan Babu, H.M. et al. A Fast FPGA-Based BCD Adder. Circuits Syst Signal Process 37, 4384–4408 (2018). https://doi.org/10.1007/s00034-018-0770-3

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Keywords

  • Adder
  • BCD
  • FPGA
  • LUT
  • Correction