Circuits, Systems, and Signal Processing

, Volume 37, Issue 10, pp 4384–4408 | Cite as

A Fast FPGA-Based BCD Adder

  • Mubin Ul Haque
  • Zarrin Tasnim Sworna
  • Hafiz Md. Hasan BabuEmail author
  • Ashis Kumer Biswas


The binary-coded decimal (BCD) being the more accurate and human-readable representation with ease of conversion is prevailing in the computing and electronic communication. In this paper, a tree-structured parallel BCD addition algorithm is proposed with the reduced time complexity \(O(N(\log _2b)+(N-1))\), where N = number of digits and b = number of bits in a digit. BCD adder is more effective with a lookup table (LUT)-based design, due to field programmable gate array (FPGA) technology’s enumerable benefits and applications. A size-minimal and depth-minimal LUT-based BCD adder circuit construction is the main contribution of this paper. The proposed parallel BCD adder gains a radical achievement compared to the existing best known LUT-based BCD adders. The proposed BCD adder is coded in VHDL and implemented in a Virtex-6 platform targeting XC6VLX75T Xilinx FPGA with a \(-3\) speed grade by using ISE 13.1. The proposed BCD adder provides prominent better performance with 20.0% reduction in area and 41.32% reduction in delay for the post-layout simulation. Since the proposed circuit is improved in both area and delay parameter, it is 53.06% efficient in terms of area-delay product compared to the best known existing BCD adder, which is surely a significant achievement. Moreover, the proposed design consumes 34.28% less power in comparison with existing best known approach at a clock frequency of 200 MHz and a reference voltage of 5 V.


Adder BCD FPGA LUT Correction 


  1. 1.
    O. Al-Khaleel, M. Al-Khaleel, Z. Al-QudahJ, C.A. Papachristou, K. Mhaidat, F.G. Wolff, Fast binary/decimal adder/subtractor with a novel correction-free bcd addition, in 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, pp. 455–459 (2011)Google Scholar
  2. 2.
    O.D. Al-Khaleel, N.H. Tuli, K.M. Mhaidat, Fpga implementation of binary coded decimal digit adders and multipliers, in 2012 8th International Symposium on Mechatronics and its Applications, pp. 1–5 (2012)Google Scholar
  3. 3.
    A. Benoit, H. Larchevque, P. Renaud-Goud, Optimal algorithms and approximation algorithms for replica placement with distance constraints in tree networks, in 2012 IEEE 26th International Parallel and Distributed Processing Symposium, pp. 1022–1033 (2012)Google Scholar
  4. 4.
    G. Bioul, M. Vazquez, J.P. Deschamps, G. Sutter, Decimal addition in fpga, in 5th Southern Conference on Programmable Logic, 2009. SPL (IEEE, 2009), pp. 101–108Google Scholar
  5. 5.
    G. Bioul, M. Vazquez, J.P. Deschamps, G. Sutter, High-speed fpga 10’s complement adders–subtractors. Int. J. Reconfig. Comput. 2010, 4:2 (2010)CrossRefGoogle Scholar
  6. 6.
    S. Gao, D. Al-Khalili, N. Chabini, An improved bcd adder using 6-lut fpgas, in: 10th IEEE International NEWCAS Conference, pp. 13–16 (2012)Google Scholar
  7. 7.
    L. Han, S.B. Ko, High-speed parallel decimal multiplication with redundant internal encodings. IEEE Trans. Comput. 62(5), 956–968 (2013)MathSciNetCrossRefzbMATHGoogle Scholar
  8. 8.
    Inc (Si2) Silicon Integration Initiative, Cmos 45 nm open cell library, in Access date: 14 March (2017)
  9. 9.
    S. Mishra, G. Verma, Low power and area efficient implementation of bcd adder on fpga, in: 2013 International Conference on Signal Processing and Communication (ICSC) (IEEE, 2013), pp. 461–465Google Scholar
  10. 10.
    Y. Ning, Z. Guo, S. Shen, B. Peng, Design of data acquisition and storage system based on the fpga, in Procedia Engineering. International Workshop on Information and Electronics Engineering, vol. 29, pp. 2927–2931 (2012)Google Scholar
  11. 11.
    J.M. Pierre Langlois, S. Gao, D. Al-Khalili, N. Chabini, Efficient realization of bcd multipliers using fpgas. Int. J. Reconfig. Comput. 2017, 2927–2931 (2017)Google Scholar
  12. 12.
    K. Pocek, R. Tessier, A. DeHon, Birth and adolescence of reconfigurable computing: a survey of the first 20 years of field-programmable custom computing machines, in 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines, pp. 1–17 (2013)Google Scholar
  13. 13.
    C. Sundaresan, C.V.S. Chaitanya, P.R. Venkateswaran, S. Bhat, J. Mohan Kumar, High speed bcd adder, in Proceedings of the 2011 2nd International Congress on Computer Applications and Computational Science ed. by F.L. Gaol, Q.V. Nguyen (Springer, Berlin 2012), pp. 113–118Google Scholar
  14. 14.
    G. Sutter, E. Todorovich, G. Bioul, M. Vazquez, J.P. Deschamps, Fpga implementations of bcd multipliers, in 2009 International Conference on Reconfigurable Computing and FPGAs, pp. 36–41 (2009)Google Scholar
  15. 15.
    Z.T. Sworna, M. Ul Haque, H.M. Hasan Babu, A lut-based matrix multiplication using neural networks, in 2016 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1982–1985 (2016)Google Scholar
  16. 16.
    Z.T. Sworna, M. Ul Haque, N. Tara, H.M. Hasan Babu, A.K. Biswas, Low-power and area efficient binary coded decimal adder design using a look up table-based field programmable gate array. IET Circuits Devices Syst. 10(3), 163–172 (2016)CrossRefGoogle Scholar
  17. 17.
    A. Vazquez, F. De Dinechin, Multi-operand decimal adder trees for FPGAs. Ph.D. thesis, INRIA (2010)Google Scholar
  18. 18.
    M. Vazquez, G. Sutter, G. Bioul, J.-P. Deschamps, Decimal adders/subtractors in fpga: efficient 6-input lut implementations, in International Conference on Reconfigurable Computing and FPGAs, 2009. ReConFig’09 (IEEE, 2009), pp. 42–47Google Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  • Mubin Ul Haque
    • 1
  • Zarrin Tasnim Sworna
    • 1
  • Hafiz Md. Hasan Babu
    • 1
    Email author
  • Ashis Kumer Biswas
    • 2
  1. 1.University of DhakaDhakaBangladesh
  2. 2.The University of Colorado DenverDenverUSA

Personalised recommendations