Abstract
Residue number system is a non-weighted system in which some arithmetic operations are performed parallelly. A factor that affects the system’s performance is the complexity of converters, as the complexity of reverse converter should not discomfit the earned speed of parallelly performing arithmetic unit. In this paper, two efficient reverse converters are proposed for moduli set \(\{2^{2n+1}-1,2^{2n},2^{n}-1\}\) by using two-level method and mixed-radix conversion algorithm. Both unit gate model and simulation are used to have an efficient comparison. The novel converters and the recently presented reverse converters with similar dynamic range were implemented in Hardware Description Language on Xilinx 13.1 FPGA simulator. Area and delay of each converter were measured for various dynamic range up to 256 bits. As the results indicated, the novel proposed area-efficient converter and delay-efficient converter indicate an improvement about 8 and 14%, respectively, in terms of time complexity comparing to the recently presented design.
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SalehiTabrizi, N., TaghipourEivazi, S. Designing Efficient Two-Level Reverse Converters for Moduli Set \(\{2^{2n+1}-1,2^{2n},2^{n}-1\}\). Circuits Syst Signal Process 37, 4162–4180 (2018). https://doi.org/10.1007/s00034-018-0756-1
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DOI: https://doi.org/10.1007/s00034-018-0756-1