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A Reduced Hardware ISI and Mismatch Shaping DEM Decoder

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Abstract

This paper presents a dynamic element matching (DEM) decoder incorporating both intersymbol interference (ISI) and mismatch error shaping. From the analysis of ISI error in multi-bit DACs, an algorithm is developed that deterministically controls the element transitions, such that on each conversion cycle the instantaneous number of on transitions is set to a constant value, while the instantaneous number of off transitions varies with the decoder input signal. The technique achieves greater ISI error mitigation than previous approaches using less hardware. To further reduce the logic area, a hierarchical DEM structure, whereby the DEM decoder is split into multiple sub-DEM decoders, is presented.

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  • 01 December 2017

    The original version of the article unfortunately contained an error in figure. The presentation of Fig. 2 is incorrect. Figure 1 was erroneously duplicated and published as Fig. 2 in the article.

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Acknowledgements

This work has been supported by Enterprise Ireland, Innovation Partnership Project IP/2013/0271 co-funded by the Irish Government and the EU European Regional Development Fund (ERDF). The authors are grateful to the funding agency Enterprise Ireland for enabling this research in collaboration with our partner Analog Devices, Limerick, Ireland.

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Authors and Affiliations

  1. University of Limerick, Limerick, Ireland

    Vincent O’Brien, Anthony G. Scanlan & Brendan Mullane

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  1. Vincent O’Brien
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  2. Anthony G. Scanlan
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  3. Brendan Mullane
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Correspondence to Vincent O’Brien.

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O’Brien, V., Scanlan, A.G. & Mullane, B. A Reduced Hardware ISI and Mismatch Shaping DEM Decoder. Circuits Syst Signal Process 37, 2299–2317 (2018). https://doi.org/10.1007/s00034-017-0681-8

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  • DOI: https://doi.org/10.1007/s00034-017-0681-8

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