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Analysis and Design of Single Reference Reduced Summer Loading-Based Switched Capacitor DFE

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Abstract

Decision feedback equalizers (DFE) are an integral part of modern serial link receivers. Attenuation in wireline communication channels causes pulse spreading. Hence, multi-tap post-cursor cancellation is necessary for reliable recovery of data at the receiver. However, the addition of multiple taps causes loading on the analog summing node which degrades the bandwidth of operation. This paper explores the design parameters of a switched capacitor-based DFE for multi-tap post-cursor cancellation with reduced summer loading. The architecture is validated by post-layout simulations done in UMC65SP technology. A PRBS-7 generator is used, and test cases are simulated upto 4.0 Gbps for two different channel attenuations around 20 dB.

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Notes

  1. The proposed architecture was completely realized using parametric capacitors. Custom MOM capacitors that can realize capacitance values \(<~1\) fF could also be used.

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Authors and Affiliations

  1. Department of ECE, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Kollam, 690525, India

    Nevin Alex Jacob

  2. University of Illinois at Urbana-Champaign, Urbana, IL, 61801, USA

    Bibhudatta Sahoo

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  1. Nevin Alex Jacob
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  2. Bibhudatta Sahoo
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Correspondence to Bibhudatta Sahoo.

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Jacob, N.A., Sahoo, B. Analysis and Design of Single Reference Reduced Summer Loading-Based Switched Capacitor DFE. Circuits Syst Signal Process 36, 4994–5018 (2017). https://doi.org/10.1007/s00034-017-0664-9

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  • DOI: https://doi.org/10.1007/s00034-017-0664-9

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