Design of Low-Power High-Performance FinFET Standard Cells
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With the leakage power becoming a most important concern in deep sub-micron designs, the advent of FinFET offers promising options due to its superior electrical properties and design flexibility. To support the VLSI digital system design flow based on the standard cells in FinFET, the building method of optimized FinFET standard cells is proposed. This method is derived on the basis of jointly optimizing the back-gate voltages and the width to length ratio of the transistors in the stacked structure in each standard cell under the premise of maintaining the performance. By employing this design method, optimized standard cells are generated and form a low-power high-performance standard cell library. Simulation results of the standard cells designed with our proposed method demonstrate that the leakage power can be reduced by a factor of 47.99 at most while the worst-case delay can achieve a maximum reduction of 10.17%. Monte Carlo simulation results illustrate that the optimized cells can gain more dependability to process variations and environmental changes. The 16-bit ripple carry adder implemented with this optimized FinFET library can obtain a maximum leakage power reduction of 59.6% and a worst-case delay reduction of 21.8%.
KeywordsVLSI FinFET Standard cell Stacking Back-gate biasing Width to length ratio
This work was supported by Beijing Natural Science Foundation (Grant No. 4152020), National Natural Science Foundation of China (Grant No. 61306040), State Key Development Program for Basic Research of China (973) (Grant No. 2015CB057201), Natural Science Foundation of Guangdong Province, China (Grant No. 2015A030313147) and the R&D project of Shenzhen Government, China (Grant Nos. JCYJ20170412150411676, JCYJ20160229122349365).
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