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Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA

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Abstract

In today’s world, high-power computing applications such as image processing, digital signal processing, graphics, robotics require enormous computing power. These applications use matrix operations, especially matrix multiplication. Multiplication operations require a lot of computational time and are also complex in design. We can use field-programmable gate arrays as low-cost hardware accelerators along with a low-cost general-purpose processor instead of a high-cost application-specific processor for such applications. In this work, we employ an efficient Strassen’s algorithm for matrix multiplication and a highly efficient run-time-reconfigurable floating-point multiplier for matrix element multiplication. The run-time-reconfigurable floating-point multiplier is implemented with custom floating-point format for variable-precision applications. A very efficient combination of Karatsuba algorithm and Urdhva Tiryagbhyam algorithm is used to implement the binary multiplier. This design can effectively adjust the power and delay requirements according to different accuracy requirements by reconfiguring itself during run time.

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  1. School of VLSI Design and Embedded Systems, National Institute of Technology Kurukshetra, Kurukshetra, Haryana, India

    S. Arish & R. K. Sharma

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  1. S. Arish
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  2. R. K. Sharma
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Correspondence to S. Arish.

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Arish, S., Sharma, R.K. Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA. Circuits Syst Signal Process 36, 998–1026 (2017). https://doi.org/10.1007/s00034-016-0335-2

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