Abstract
Comparators are the main components in several analog and mixed-signal systems. Design and synthesis of comparator architectures largely remain an analog designer’s art. In this work, we present a systematic methodology for designing comparators using the method of constrained optimization. Constrained optimization is an equation-based optimization method and requires accurate equations. We propose a new delay equation for latch-based comparators. The new delay model is based on Adomian decomposition method and gives more accurate delay characteristics compared with the conventional one. The architecture is optimized for total power dissipation with speed, area and noise as the constraints. Geometric programming-based automation algorithm and the behavioral model of the comparator architecture are written in MATLAB. The optimized schematic is drawn in Cadence 180 nm technology, and the results are verified with MATLAB.
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References
G. Adomian, Solving Frontier Problems of Physics: The Decomposition Method (Kluwer, Dordrecht, 1994)
C. Bamji, M. Borah, An Improved Cost Heuristic for Transistor Sizing, in Proceedings of International Conference on VLSI Design (1998), pp. 534–539
M. Blesken, U. Ruckert, D. Steenken, K. Witting, M. Dellnitz, Multiobjective optimization for transistor sizing of CMOS logic standard cells using set oriented numerical techniques, in Proceedings of NORCHIP (2009), pp. 1–4
M. Borah, R.M. Owens, M.J. Irwin, Transistor sizing for low power CMOS circuits. IEEE Trans. Comput. Aided Design Integr. Circuits Syst. 15, 665–671 (1996)
S.P. Boyd, S.-J. Kim, S. Mohan, Geometric programming and its applications to EDA problems, in Design and Test in Europe (DATE) 2005 Tutorial. Available at www.stanford.edu/boyd/date05.html
L.R. Carley, R.A. Rutenbar, How to automate analog IC designs, in IEEE Spectrum (1988), pp. 26–30
E.K.P. Chong, S.H. Zak, An Introduction to Optimization (Wiley, New York, 1996)
S. Dasgupta, P. Mandal, An automated design approach for CMOS LDO regulators, in Proceeding of Asia and South Pacific Design Automation Conference (2009), pp. 510–515
T.R. Dastidar, P.P. Chakrabarti, P. Ray, A synthesis system for analog circuits based on evolutionary search and topological reuse. IEEE Transactions on Evolutionary Computation (2005), pp. 211–224
F. El-Turkey, E.E. Perry, BLADES: An artificial intelligence approach to analog circuit design, in IEEE Transactions Computer-Aided Design Integrated Circuits Systems (1989), pp. 680–692
M. Fakhfakh, Y. Cooren, A. Sallem, M. Loulou, P. Siarry, Analog circuit design optimization through the particle swarm optimization technique, in Proceedings of Analog Integrated Circuits and Signal Processing (2010), pp. 71–82
J. Fishburn, A. Dunlop, TILOS: a posynomial programming approach to transistor sizing, in Proceedings of IEEE International Conference on Computer Aided Design (ICCAD-85) Digest of Technical Papers (1985), pp. 326–328
G.G.E. Gielen, H.C.C. Walscharts, W.M.C. Sansen, Analog circuit design optimization based on symbolic simulation and simulated annealing. in IEEE Journal of Solid-StateCircuits (1990), pp. 707–713
M. Hershenson, S.P. Boyd, T.H. Lee, Optimal design of a CMOS Op-Amp via geometric programming. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2001), pp. 1–21
M. Hershenson, S. Mohan, S.P. Boyd, T.H. Lee, Optimization of inductor circuits via geometric programming, in Proceedings of Design Automation Conference (1999), pp. 994–998
M. Hershenson, Design of pipeline analog-to-digital converters via geometric programming, in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (2002), pp. 317–324
D.A. Johns, K. Martin, Analog Integrated Circuit Design (Wiley, New York, 1997)
P.C. Maulik, L.R. Carley, R.A. Rutenbar, Integer programming based topology selection of cell-level analog circuits. in IEEE Transactions on Computer-Aided Design Integrated Circuits and systems (1995), pp. 401–412
R. Ockey, M. Syrzycki, Optimization of a latched comparator for high-speed analog-to-digital converters, in Proceedings of the 1999 IEEE Canadian Conference on Electrical and Computer Engineering (1999), pp. 401–408
S.K. Patnaik, S. Banerjee, Noise and error analysis and optimization of a CMOS latched comparator, in International Conference on Communication Technology and System Design (2011), pp. 139–144
R. Phelps, M. Krasnicki, R.A. Rutenbar, L.R. Carley, J.R. Hellums, Anaconda: simulation based synthesis of analog circuits via stochastic pattern search. in IEEE Transactions on Computer-Aided Design Integrated Circuits System (2000), pp. 703–717
Y. Qi, G. Zhang, Z. Shao, B. Wang, A low kick-back noise latched comparator for high-speed folding and interpolating ADC, in AAPCCAS (2008), pp. 1973–1976
R.A. Rutenbar, Design automation for analog: the next generation of tool challenges, in Proceedings of ICCAD, San Jose (CA, 2006), pp. 458–460
K.D. Sadeghipour, An improved low offset latch comparator for high speed ADCs. Anal. Integr. Circuit Signal Process. 66, 205–212 (2011)
R.A. Vural, U. Bozkurt, T. Yildirim, Metaheuristics based CMOS two-stage comparator optimization, in Proceedings of the World Congress on Engineering and Computer Science (2013), pp. 645–650
M. Wang, Design optimization of CMOS CDC comparators, in International Conference on Computational Problem-Solving (2011)
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Purushothaman, A., Parikh, C.D. A New Delay Model and Geometric Programming-Based Design Automation for Latched Comparators. Circuits Syst Signal Process 34, 2749–2764 (2015). https://doi.org/10.1007/s00034-015-9988-5
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DOI: https://doi.org/10.1007/s00034-015-9988-5