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Performance Analysis of a Modified MAP Decoder Architecture for Low Power Dissipation

Abstract

A modified architecture for minimized power dissipation in the maximum a posteriori (MAP) decoder based on clock gating and toggle filtering is proposed in this paper. Log likelihood ratio (LLR) in the trellis structure of the MAP decoder consumes large power. To minimize the power dissipation, toggle-filtering technique is introduced in the LLR unit of MAP decoder and clock-gating approach is introduced in the state metric, branch metric and again in LLR blocks of the MAP decoder. Toggle filter is used to avoid early injection of signals from the state metric and branch metric units. Clock-gating approach is used to keep the idle block in the disabled state. A power dissipation of 53.64 % has been achieved when toggle-filtering technique is applied and 54.4 % when clock-gating technique is applied. Power dissipation of 64.07 % has been achieved for the combined effect of toggle-filtering and clock-gating technique.

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Acknowledgments

The authors would like to thank the anonymous reviewers, Editor-in-Chief and Associate Editor for their constructive comments which helped to improve the clarity and presentation of the paper.

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Correspondence to S. Shiyamala.

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Shiyamala, S., Rajamani, V. Performance Analysis of a Modified MAP Decoder Architecture for Low Power Dissipation. Circuits Syst Signal Process 34, 3949–3964 (2015). https://doi.org/10.1007/s00034-015-0045-1

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Keywords

  • Decoder
  • Folded technique
  • Clock gating
  • Toggle filter
  • Power dissipation