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Lookahead Architectures for Hamming Distance and Fixed-Threshold Hamming Weight Comparators

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Abstract

A Hamming distance comparator (also known as \(k\)-order comparator) compares its two operands and outputs an agreement if they differ in less than \(k\) corresponding bits. In this paper, we introduce novel architectures for the design of Hamming distance \(k\) comparators, for the usually adopted values 2 or 3 for \(k\). The proposed architectures are fully digital and are based on splitting the difference vector in smaller groups and performing comparison against \(k\) in parallel with counting, leading to significant speedup against previous proposals. The derived architectures can also be used for fixed-threshold Hamming weight comparators for small or large threshold values. The proposed 2- and 3-order comparators are more than 60 and 31 % more efficient than the most competitive previous proposal, respectively, using the area \(\times \) time\(^2\) metric, while their total power dissipation remains low.

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References

  1. S. Abdel-Hafeez, B. Parhami, High-speed and low-power scalable Hamming weight comparator based on a non-weighted switched-capacitor array. Analog Integ. Circ. Sig. Process. 75, 417–434 (2013)

    Article  Google Scholar 

  2. C. Barral, J.-S. Coron, D. Naccache, Externalized fingerprint matching, in Biometric Authentication, Lecture Notes in Computer Science, ed. by D. Zhang, A. Jain (Springer, Berlin, 2004), pp. 309–315

    Chapter  Google Scholar 

  3. K. E. Batcher, Sorting networks and their applications, in Proceedings of the April 30–May 2, 1968, Spring joint computer conference, ser. AFIPS’68 (Spring). New York, NY, USA: ACM, 1968, pp. 307–314

  4. M. Fujino, V. Moshnyaga, in Proceedings of the 9th International Conference on Electronics, Circuits and Systems (ICECS). An efficient Hamming distance comparator for low-power applications 2, 641–644 (2002)

  5. X. Kavousianos and D. Nikolos, Self-exercising self testing k-order comparators, in Proceedings of the 15th IEEE VLSI Test Symposium, 1997, pp. 216–221

  6. D.B.S. King et al., Digital n-tuple Hamming comparator for weightless systems. Electron. Lett. 34(22), 2103–2104 (1998)

    Article  Google Scholar 

  7. T. Koide et al. A nearest-Hamming-distance search memory with fully parallel mixed digital-analog match circuitry, in Proceedings of the 2003 Asia and South Pacific Design Automation Conference, (ASP-DAC), 2003, pp. 591–592

  8. V. A. Kulyukin and A. Bookstein, Integrated object recognition with extended Hamming distance, in Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing, 1995

  9. H. Mattausch et al., Associative memory for nearest-Hamming-distance search based on frequency mapping. IEEE J. Solid-State Circuits 47(6), 1448–1459 (2012)

    Article  Google Scholar 

  10. B. Parhami, Efficient Hamming weight comparators for binary vectors based on accumulative and up/down parallel counters. IEEE Trans. Circ. Syst. II 56(2), 167–171 (2009)

    Article  Google Scholar 

  11. V. Pedroni, in Proceedings of the International Symposium on Circuits and Systems. Compact Hamming-comparator-based rank order filter for digital VLSI and FPGA implementations 2, 585–588 (2004)

  12. S. Piestrak, Efficient Hamming weight comparators of binary vectors. Electron. Lett. 43(11), 611–612 (2007)

    Article  Google Scholar 

  13. V. Sklyarov, I. Skliarova, Digital Hamming weight and distance analyzers for binary vectors and matrices. Int. J. Innov. Comput. Inf. Control 9(12), 4825–4849 (2013)

    Google Scholar 

  14. J. Stine, M. Schulte, in Proceedings of the 2005 IEEE International Symposium on Circuits and Systems. A combined two’s complement and floating-point comparator 1, 89–92 (2005)

  15. Synopsys Inc., Synopsys 32/28nm Generic Library, Available : http://www.synopsys.com/Community/UniversityProgram (2013)

  16. Synopsys Inc., Synopsys Design Compiler and Power Compiler, version G-2012.06.

  17. A. Tyagi, A reduced-area scheme for carry-select adders. IEEE Trans. Comput. 42(10), 1163–1170 (1993)

    Article  Google Scholar 

  18. O. Unsal et al., Impact of parameter variations on circuits and microarchitecture. IEEE Micro 26(6), 30–39 (2006)

    Article  Google Scholar 

  19. H.T. Vergos, D. Nikolos, Efficient fault tolerant cache memory design. Microprocess. Microprogram. 41(2), 153–169 (1995)

    Article  Google Scholar 

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Vergos, H.T., Bakalis, D. & Anastasiou, A. Lookahead Architectures for Hamming Distance and Fixed-Threshold Hamming Weight Comparators. Circuits Syst Signal Process 34, 1041–1056 (2015). https://doi.org/10.1007/s00034-014-9891-5

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  • DOI: https://doi.org/10.1007/s00034-014-9891-5

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