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Lector with Footed-Diode Inverter: A Technique for Leakage Reduction in Domino Circuits

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Abstract

Leakage power consumption is a major technical problem faced in nanometer or deep submicron CMOS circuit technology. A new circuit technique based on “lector stacking” is proposed in this paper for reducing the subthreshold and gate oxide leakage currents in the idle and non-idle modes of operation for domino circuits. In this technique a p-type and an n-type leakage control transistor (LCT) are introduced between the pull-up and pull-down network, and the gate of one is controlled by the source of the other. For any combination of inputs, one of the LCTs will operate near its cut-off region and will increase the resistance between supply voltage and ground, resulting in reduced leakage current. Lector stacking retains the logic state during the idle mode as in the conventional footerless domino logic. Furthermore, the leakage current is suppressed at the output inverter circuit by adding a diode-footed transistor below the n-type transistor of the inverter, offering a more resistive path between supply voltage and ground.The proposed circuit technique for AND2, OR2, OR4, and OR8 circuits reduces the active power consumption by 13.66 % to 44.45 % and by 12 % to 33 % at the low and high die temperatures, respectively, compared to the standard footerless domino logic circuits. During idle mode for the same logic gates, 1.64 % to 79.39 % and 1.2 % to 35.19 % reduction of leakage current is observed with low and high inputs at 25 °C and 110 °C respectively. Similarly, during non-idle mode 0.94 % to 99.3 % and 1.57 % to 98.58 % is observed with low and high inputs at 25 to 110 °C, respectively, when compared to standard footerless domino logic circuits.

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  1. ECE Department, Maulana Azad National Institute of Technology, Bhopal, India

    Tarun K. Gupta & Kavita Khare

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  1. Tarun K. Gupta
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  2. Kavita Khare
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Correspondence to Tarun K. Gupta.

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Gupta, T.K., Khare, K. Lector with Footed-Diode Inverter: A Technique for Leakage Reduction in Domino Circuits. Circuits Syst Signal Process 32, 2707–2722 (2013). https://doi.org/10.1007/s00034-013-9615-2

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  • DOI: https://doi.org/10.1007/s00034-013-9615-2

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