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Comparison of DEM and BEET Linearization Techniques for Flash Analog-to-Digital Converters

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Abstract

Data converter linearization has been a subject of some interest for most of the past decade. New methods of linearizing analog-to-digital converters (ADCs) continue to be developed. Various linearization methods are available but their comparative strengths and weaknesses are not easily recognizable, making it somewhat difficult to determine which compensator would provide maximum benefit for a specific device. This paper provides a novel performance comparison of two promising real-time linearization methods for flash ADCs: the in-device DEM method, and the peripherally-implemented BEET method using SFDR, SINAD, ENOB, and THD as performance metrics. It is found that BEET is the superior compensator for devices with INL values larger than 0.25 LSB and DNL values larger than 0.25 LSB for optimal SFDR. Results from SINAD, ENOB, and THD metrics indicate that BEET is superior compared to DEM for all devices that have INL>0.05 LSB.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Dayton, 300 College Park, Dayton, 45469, OH, USA

    Eric J. Balster

  2. University of Dayton Research Institute, 300 College Park, Dayton, 45469, OH, USA

    Christopher D. McGuinness & Frank A. Scarpino

Authors
  1. Christopher D. McGuinness
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  2. Eric J. Balster
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  3. Frank A. Scarpino
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Correspondence to Christopher D. McGuinness.

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McGuinness, C.D., Balster, E.J. & Scarpino, F.A. Comparison of DEM and BEET Linearization Techniques for Flash Analog-to-Digital Converters. Circuits Syst Signal Process 32, 2639–2652 (2013). https://doi.org/10.1007/s00034-013-9603-6

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  • DOI: https://doi.org/10.1007/s00034-013-9603-6

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