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DLPA: Discrepant Low PDP 8-Bit Adder

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Abstract

This paper presents a new 8-bit adder circuit, called discrepant low PDP 8-bit adder (DLPA) based on three new full adder cells, which have been designed based on requirements of different positions in each 8-bit adder circuit. In order to design the full adder cells, a new and general method has been proposed aiming to achieve full-swing output and low number of transistors. The proposed adder along with several state-of-the-art adders from the literature have been extensively analyzed and compared together. The results revealed that the power-delay product of DLPA is almost more than 20 % less than that of other compared circuits.

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Authors and Affiliations

  1. Department of Computer Engineering, Arak Branch, Islamic Azad University, Arak, Iran

    Mahdiar Ghadiry

  2. Department of Computer Engineering, Ashtian Branch, Islamic Azad University, Ashtian, Iran

    Mahdieh Nadi

  3. Faculty of Electronic Engineering, Universiti Teknologi Malaysia, Skudai, Malaysia

    Abu Khari A’Ain

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  1. Mahdiar Ghadiry
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  2. Mahdieh Nadi
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  3. Abu Khari A’Ain
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Correspondence to Mahdiar Ghadiry.

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Ghadiry, M., Nadi, M. & A’Ain, A.K. DLPA: Discrepant Low PDP 8-Bit Adder. Circuits Syst Signal Process 32, 1–14 (2013). https://doi.org/10.1007/s00034-012-9438-6

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  • DOI: https://doi.org/10.1007/s00034-012-9438-6

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