Circuits, Systems, and Signal Processing

, Volume 31, Issue 5, pp 1631–1652 | Cite as

Design and Evaluation of CNFET-Based Quaternary Circuits

  • Mohammad Hossein Moaiyeri
  • Keivan Navi
  • Omid Hashemipour


This paper presents novel high-performance and PVT tolerant quaternary logic circuits as well as efficient quaternary arithmetic circuits for nanoelectronics. These Carbon Nanotube FET (CNFET)-based circuits are compatible with the recent technologies and are designed based on the conventional CMOS architecture, while the previous quaternary designs used methods which are not suitable for nanoelectronics and have become obsolete. The proposed designs are robust and have large noise margins and high driving capability. The singular characteristics of CNFETs, such as the capability of having the desired threshold voltage by regulating the diameters of the nanotubes, make them very appropriate for voltage-mode multiple-threshold circuits design. The proposed circuits are examined, using Synopsys HSPICE with the standard 32 nm-CNFET technology in various situations and different supply voltages. Simulation results demonstrate the correct and high-performance operation of the proposed circuits even in the presence of process, voltage and temperature variations.


Carbon nanotube FET (CNFET) Quaternary logic Arithmetic and logic circuits Multiple-Vth design Nanoelectronics 


  1. 1.
    G. Cho, Y.-B. Kim, F. Lombardi, M. Choi, Performance evaluation of CNFET-based logic gates, in Proc IEEE International Instrumentation and Measurement Technology Conference, 5–7 May (2009), pp. 909–912 Google Scholar
  2. 2.
    R.C.G. Da Silva, H. Boudinov, L. Carro, A novel voltage-mode CMOS quaternary logic design. IEEE Trans. Electron Devices 53(6), 1480–1483 (2006) CrossRefGoogle Scholar
  3. 3.
    S.R.P.R. Datla, M.A. Thornton, Quaternary voltage-mode logic cells and fixed-point multiplication circuits, in Proc. IEEE International Symposium on Multiple-Valued Logic, 26–28 May (2010), pp. 128–133 CrossRefGoogle Scholar
  4. 4.
    J. Deng, Device modeling and circuit performance evaluation for nanoscale devices: silicon technology beyond 45 nm node and carbon nanotube field effect transistors. Doctoral Dissertation. Stanford University, 2007 Google Scholar
  5. 5.
    J. Deng, H.-S.P. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part I: model of the intrinsic channel region. IEEE Trans. Electron Devices 54(12), 3186–3194 (2007) CrossRefGoogle Scholar
  6. 6.
    J. Deng, H.-S.P. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part II: Full device model and circuit performance benchmarking. IEEE Trans. Electron Devices 54(12), 3195–3205 (2007) CrossRefGoogle Scholar
  7. 7.
    E. Dubrova, Multiple-valued logic in VLSI: challenges and opportunities, in Proc 17th NORCHIP Conference, Nov. (1999), pp. 340–350 Google Scholar
  8. 8.
    A. Hueng, H.T. Mouftah, Depletion/enhancement CMOS for a low power family of three-valued logic circuits. IEEE J. Solid-State Circuits 20(2), 609–616 (1985) CrossRefGoogle Scholar
  9. 9.
    S.L. Hurst, Multiple-valued logic—its status and its future. IEEE Trans. Comput. 33(12), 1160–1179 (1984) CrossRefGoogle Scholar
  10. 10.
    P. Keshavarzian, K. Navi, Universal ternary logic circuit design through carbon nanotube technology. Int. J. Nanotechnol. 6(10–11), 942–953 (2009) CrossRefGoogle Scholar
  11. 11.
    Y.-B. Kim, Challenges for nanoscale MOSFETs and emerging nanoelectronics. Trans. Electr. Electron. Mater. 11(3), 93–105 (2010) CrossRefGoogle Scholar
  12. 12.
    Y.B. Kim, Y.-B. Kim, F. Lombardi, Novel design methodology to optimize the speed and power of the CNTFET circuits, in Proc IEEE International Midwest Symposium on Circuits and Systems, 2–5 Aug. (2009), pp. 1130–1133 CrossRefGoogle Scholar
  13. 13.
    Y. Li, W. Kim, Y. Zhang, M. Rolandi, D. Wang, Growth of single-walled carbon nanotubes from discrete catalytic nanoparticles of various sizes. J. Phys. Chem. B 105(46), 11424–11431 (2001) CrossRefGoogle Scholar
  14. 14.
    A. Lin, N. Patil, K. Ryu, A. Badmaev, L.G. De Arco, C. Zhou, S. Mitra, H.-S.P. Wong, Threshold voltage and on–off ratio tuning for multiple-tube carbon nanotube FETs. IEEE Trans. Nanotechnol. 8(1), 4–9 (2009) CrossRefGoogle Scholar
  15. 15.
    S. Lin, Y.-B. Kim, F. Lombardi, A novel CNFET based ternary logic gate design, in Proc IEEE International Midwest Symposium on Circuits and Systems, 2–5 Aug. (2009), pp. 435–438 CrossRefGoogle Scholar
  16. 16.
    S. Lin, Y.-B. Kim, F. Lombardi, Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability. Integr. VLSI J. 43(2), 176–187 (2010) CrossRefGoogle Scholar
  17. 17.
    S. Lin, Y.-B. Kim, F. Lombardi, CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE Trans. Nanotechnol. 10(2), 217–225 (2011) CrossRefGoogle Scholar
  18. 18.
    P.L. McEuen, M. Fuhrer, H. Park, Single-walled carbon nanotube electronics. IEEE Trans. Nanotechnol. 1(1), 78–85 (2002) CrossRefGoogle Scholar
  19. 19.
    M.H. Moaiyeri, A. Doostaregan, K. Navi, Design of energy-efficient and robust ternary circuits for nanotechnology. IET Circuits Devices Syst. 5(4), 285–296 (2011) CrossRefGoogle Scholar
  20. 20.
    M.H. Moaiyeri, R. Chavoshisani, A. Jalali, K. Navi, O. Hashemipour, High-performance mixed-mode universal min-max circuits for nanotechnology. Circuits Syst. Signal Process. 31(2), 465–488 (2012) MathSciNetCrossRefGoogle Scholar
  21. 21.
    H.T. Mouftah, I.B. Jordan, Integrated circuits for ternary logic, in Proc. International Symposium on Multiple Valued Logic, May (1974), pp. 285–302 Google Scholar
  22. 22.
    H.T. Mouftah, K.C. Smith, Injected voltage low-power CMOS for 3-valued logic. IEE Proc. G, Electron. Circuits Syst. 129(6), 270–272 (1982) CrossRefGoogle Scholar
  23. 23.
    K. Navi, M.H. Moaiyeri, R. Faghih Mirzaee, O. Hashemipour, B. Mazloom Nezhad, Two new low-power full adders based on majority-not gates. Microelectron. J. 40(1), 126–130 (2009) CrossRefGoogle Scholar
  24. 24.
    K. Navi, A. Doostaregan, M.H. Moaiyeri, O. Hashemipour, A hardware-friendly arithmetic method and efficient implementations for designing digital fuzzy adders. Fuzzy Sets Syst. 185(1), 111–124 (2011) MathSciNetzbMATHCrossRefGoogle Scholar
  25. 25.
    Y. Ohno, S. Kishimoto, T. Mizutani, T. Okazaki, H. Shinohara, Chirality assignment of individual single-walled carbon nanotubes in carbon nanotube field-effect transistors by micro-photocurrent spectroscopy. Appl. Phys. Lett. 84(8), 1368–1370 (2004) CrossRefGoogle Scholar
  26. 26.
    N. Patil, A. Lin, J. Zhang, H. Wei, K. Anderson, H.-S.P. Wong, S. Mitra, Scalable carbon nanotube computational and storage circuits immune to metallic and mispositioned carbon nanotubes. IEEE Trans. Nanotechnol. 10(4), 744–750 (2011) CrossRefGoogle Scholar
  27. 27.
    A. Raychowdhury, K. Roy, Carbon-nanotube-based voltage-mode multiple-valued logic design. IEEE Trans. Nanotechnol. 4(2), 168–179 (2005) CrossRefGoogle Scholar
  28. 28.
    A. Raychowdhury, K. Roy, Carbon nanotube electronics: design of high-performance and low-power digital circuits. IEEE Trans. Circuits Syst. 54(11), 2391–2401 (2007) CrossRefGoogle Scholar
  29. 29.
    H. Shahidipour, A. Ahmadi, K. Maharatna, Effect of variability in SWCNT-based logic gates, in Proc International Symposium on Integrated Circuits, 14–16 Dec. (2009), pp. 252–255 Google Scholar
  30. 30.
    A. Srivastava, Back gate bias method of threshold voltage control for the design of low voltage CMOS ternary logic circuits. Microelectron. Reliab. 40(12), 2107–2110 (2000) CrossRefGoogle Scholar
  31. 31.
    A. Srivastava, K. Venkatapathy, Design and implementation of a low power ternary full adder. VLSI Des. 4(1), 75–78 (1996) CrossRefGoogle Scholar
  32. 32.
    M.A. Tehrani, F. Safaei, M.H. Moaiyeri, K. Navi, Design and implementation of multi-stage interconnection networks using quantum-dot cellular automata. Microelectron. J. 42(6), 913–922 (2011) CrossRefGoogle Scholar
  33. 33.
    I. Thoidis, D. Soudris, I. Karafyllidis, S. Christoforidis, A. Thanailakis, Quaternary voltage-mode CMOS circuits for multiple-valued logic. IEE Proc., Circuits Devices Syst. 145(2), 71–77 (1998) CrossRefGoogle Scholar
  34. 34.
    P.K.S. Vasundara, K.S. Gurumurthy, Quaternary CMOS combinational logic circuits, in Proc. IEEE International Conference on Information and Multimedia Technology, 16–18 Dec. (2009), pp. 538–542 Google Scholar
  35. 35.
    B. Wang, P. Poa, L. Wei, L. Li, Y. Yang, Y. Chen, (n,m) selectivity of single-walled carbon nanotubes by different carbon precursors on Co-Mo catalysts. J. Am. Chem. Soc. 129(9), 9014–9019 (2007) CrossRefGoogle Scholar
  36. 36.
    Y. Yasuda, Y. Tokuda, S. Zaima, K. Pak, T. Nakamura, A. Yoshida, Realization of quaternary logic circuits by n-channel MOS devices. IEEE J. Solid-State Circuits SC-21(1), 162–168 (1986) CrossRefGoogle Scholar
  37. 37.
    J. Zhang, N. Patil, A. Lin, H.-S.P. Wong, S. Mitra, Carbon nanotube circuits: living with imperfections and variations, in Proc. Design, Automation & Test in Europe Conference & Exhibition (DATE), 8–12 Mar. (2010), pp. 1159–1164 Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2012

Authors and Affiliations

  • Mohammad Hossein Moaiyeri
    • 1
    • 2
    • 3
  • Keivan Navi
    • 1
    • 2
  • Omid Hashemipour
    • 1
    • 3
  1. 1.Faculty of Electrical and Computer EngineeringShahid Beheshti University, G. C.TehranIran
  2. 2.Nanotechnology and Quantum Computing LabShahid Beheshti University, G. C.TehranIran
  3. 3.Microelectronics LabShahid Beheshti University, G. C.TehranIran

Personalised recommendations