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Minimizing Register Requirements of a Modulo Schedule via Optimum Stage Scheduling

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Abstract

Modulo scheduling is an efficient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirements. We present an approach that schedules the loop operations for minimum register requirements, given a modulo reservation table. Our method determines optimal register requirements for machines with finite resources and for general dependence graphs. Measurements on a benchmark suite of 1327 loops from the Perfect Club, SPEC-89, and the Livermore Fortran Kernels show that the register requirements decrease by 24.8% on average when applying the optimal stage scheduler to the MRT-schedules of a register-insensitive modulo scheduler.

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Authors and Affiliations

  1. Advanced Computer Architecture Laboratory, EECS Department, University of Michigan, 1301 Beal Avenue, Ann Arbor, Michigan, 48109-2122, USA

    Alexandre E. Eichenberger & Edward S. Davidson

  2. Hewlett Packard Laboratories, 1501 Page Mill Road, Palo Alto, California, 94304, USA

    Santosh G. Abraham

Authors
  1. Alexandre E. Eichenberger
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  2. Edward S. Davidson
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  3. Santosh G. Abraham
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Correspondence to Alexandre E. Eichenberger.

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Eichenberger, A.E., Davidson, E.S. & Abraham, S.G. Minimizing Register Requirements of a Modulo Schedule via Optimum Stage Scheduling. Int J Parallel Prog 24, 103–132 (1996). https://doi.org/10.1007/BF03356744

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  • DOI: https://doi.org/10.1007/BF03356744

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