Pinholes on thermally grown oxide under polysilicon layer after plasma etching

Abstract

Pinholes on the thermally grown oxide, which is called gate oxide, on silicon substrate under polysilicon layer are observed and its mechanism is analyzed in this paper. The oxide under a polysilicon layer is broken during the plasma etching process of other polysilicon layer. Both polysilicon layers are separated with 0.8 μm thick oxide deposited by CVD (Chemical Vapor Deposition). Since broken oxide points are found scattered around an arc occurrence point, it is assumed that an extremely high electric field generated near the arc occurrence point breaks the gate oxide. The arc occurrence point has been observed on the alignment key and is the mark of low yield. It is found that any arc occurrence can cause chips to fail by breaking the gate oxide, even if arc occurrence points are found on the scribeline.