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Übersetzung von Datenflußgraphen in optimierte Assemblerprogramme für Signalprozessoren

Transformation of data flow graphs into optimized assembly programs for signal processors

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Zusammenfassung

Die Synthese effizienter Programme für digitale Signalprozessoren mit heterogener Registerarchitektur stellt nach wie vor cine Herausforderung für den Compilerbau dar. In diesem Beitrag wird das Konzept eines Datenflußgraph-Compilers für digitale Signalprozessoren vorgestellt. Die Transformation von Datenflußgraphen in Trellis-Bäume — über den Zwischenschritt der eingeschränkten Bäume — erlaubt die Erzeugung von sequentiellem Zwischencode mittels eines Algorithmus, dessen Komplexität nur linear von der Größe des Datenflußgraphen abhängt. In einem anschließenden Schritt werden die Register zugewiesen unter Berücksichtigung der Einschränkungen durch Mehrfachbefehle. Die Ausführungszeit des resultierenden Assemblerprogramms wird durch Parallelisierung auf Befehlsebene und Optimierung des Speicher-Layouts minimiert.

Abstract

The synthesis of efficient programs for digital signal processors with non-homogeneous register sets is still a challenge of compiler design. In this paper, we introduce the concept of a data flow graph compiler for digital signal processors. In a first step, the data flow graph is decomposed into constrained expression trees and represented by trellis trees, which allows to apply a straight-line code generation algorithm whose complexity depends just linearly on the size of the graph. Registers are assigned by taking into account the constraints of multi-function instructions. The execution time of the resulting assembly code is minimized by exploiting instruction level parallelism and memory layout optimizations.

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Authors and Affiliations

  1. Institut für Nachrichtentechnik und Hochfrequenztechnik, Technische Universität Wien, Gußhausstraße 25/389, A-1040, Wien

    W. Kreuzer ÖVE, IEEE, S. Fröhlich, M. Gotschlich IEEE, A. Helm & B. Wess IEEE

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  1. W. Kreuzer ÖVE, IEEE
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  2. S. Fröhlich
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  3. M. Gotschlich IEEE
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  4. A. Helm
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  5. B. Wess IEEE
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Additional information

Herrn Professor Dr.-Ing. Dr. h.c. mult. Hans Wilhelm Schüßler zum 70. Geburtstag gewidmet.

Diese Arbeit wurde im Rahmen des FWF-Projekts P1070--ÖTE und in Zusammenarbeit mit Siemens EZM Ges.m.b.H. Villach ausgeführt.

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Kreuzer, W., Fröhlich, S., Gotschlich, M. et al. Übersetzung von Datenflußgraphen in optimierte Assemblerprogramme für Signalprozessoren. Elektrotech. Inftech. 115, 41–47 (1998). https://doi.org/10.1007/BF03159136

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