Abstract
Binary Rate Multipliers are pulse frequency converting circuits, which perform first degree or linear segment interpolations.
Here a scheme for an ideally fast rate Multiplier, different from conventional Binary Rate Multiplier, has been developed and found working satisfactorily. This scheme has been implemented by using standard digital logic modules. Errors in the multiplier and methods employed to eliminate these errors have also been discussed.
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Communicated by Prof. R. Narasimhan
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Vasantha, S. High speed binary rate multiplier. Proc. Indian Acad. Sci. 65, 340–348 (1967). https://doi.org/10.1007/BF03054095
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DOI: https://doi.org/10.1007/BF03054095