Abstract
A number of data-driven execution models have been proposed for parallel execution of logic programs8, 12, 9, 3) LogDf is an abstract data-driven execution model for pure logic programs3) which has shown promising performance during simulations. However, the original model lacks support for extra logical features such as cut and side-effects, which are needed to execute Prolog programs. This paper describes a scheme that has been incorporated into the LogDf model to support cut and side-effects. The main component of the scheme is a data structure, called a flat, non-strict S-Stream, which maintains strict ordering of multiple solutions, and, at the same time, allows simultaneous modification by several actors. This ordering corresponds to the order in which solutions would be produced in a sequential system and is necessary to implement cut and side-effects. The correct synchronization and ordering of operations on the cells of an S-Stream is ensured by the use of I-structure memory.1) The descriptor based token coloring mechanism in the LogDf provides convenient support for maintaining the scope information associated with cuts. An efficient garbage collection strategy is also proposed.
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This research was supported in part by Texas Advanced Technology Program Contract 3128 (1988) and Research Grant from Texas Instruments (1988).
Dr. Surapong Auwatanamongkol: He received his Master Degree in Computer and Information Science from Georgia Institute of Technology in 1982 and a Ph. D. in Computer Science from Southern Methodist University in 1991. His research interests lie in the areas of computer architecture, parallel processing and logic programming languages. Particularly, he is interested in developing data driven architecture that can efficiently support the parallel execution of logic program with cut and side effect features. This would require a scheme to proper control the order of execution of cut and side effects in a data-driven execution environment. He is also interested in some other computation models or architectures for artificial intelligence, such as Neuron Network and Fuzzy logic system, and their relationship with logic programs. He is now an instructor of National Institute of Development and Administration in Thailand.
Dr. Andrzej Ciepielewski: He graduated from the Royal Institute of Technology in Stockholm in 1984 and joined SICS (Swedish Institute of Computer Science) in 1985 During the time in SICS he participated in the international GIGALIPS project which resulted in the Aurora or-parallel Prolog system, and spawned plenty of related research world-wide. He also participated in Esprit GP-MIMD project studying operating systems for multiprocessors. Then he joined Calrlstedt Elektronik in 1992 to lead a group of computer architects designing a distributed associative graph memory architecture. His research interests include parallel architectures for declarative languages, Graph reduction, Multi-threaded architectures and Realtime systems. In particular he is interested in resource management (scheduling, load balancing, memory management), performance monitoring and analysis, and compilation (program analysis, automatic parallelisation, grain analysis, etc).
Prasenjit Biswas, Ph. D.: He is currently the Group leader for Processor Architecture and Performance Analysis at Hitachi Microsystems, San Jose, CA. Prior to joining Hitachi in 1994, he was a senior Computer Architect with Cyrix Corporation in Richardson, TX. During 1990–1992, he was with the Parallel and Systems Architecture group of Texas Instruments, Dallas, TX. He was actively involved in research on parallel architecture and execution models for Logic Programs while he was an Assistant Professor in the Dept. of Computer Science, SMU, Dallas, TX. (1983–90) His current research interests include Superscalar/Superpipelined Computer Architectures and compiling techniques, static and dynamic scheduling for Parallel Processing, Dataflow-von Neumann Hybrid architectures and Performance Evaluation. He has more than 30 research publications and is currently co-authoring an IEEE tutorial on Architectural Support for Parallel Logic Programming. He is one of the founder members of the IEEE Symposium on Parallel and Distributed Processing and has served as the Chairman of the symposium and the steering committee.
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Auwatanamongkol, S., Ciepielewski, A. & Biswas, P. Cut and side-effects in a data-driven implementation of Prolog. New Gener Comput 12, 223–250 (1994). https://doi.org/10.1007/BF03037344
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DOI: https://doi.org/10.1007/BF03037344