Thermomechanical stability of memory package with LOC structure


The present work attempts to determine an appropriate design of double-sided adhesive tape, which plays a significant role in defining the degree of chip surface damage in a plastic LOC (lead-on-chip) package. Various tape designs were tested to determine their effectiveness in preventing thermal stress-related damage on the chip surface during temperature cycling. The experimental results indicate that the thermomechanical stability of the IC pattern is more influenced by whether the LOC tape is employed along the chip edge than by the size of the tape covering area. Moreover, it was found that chip surface damage associated with LOC tape can be caused by normal stress applied to the chip surface vertically as well as by shear stress, which is known to cause damage. The importance of the normal stress component is verified through a 3-dimensional FEM (finite element method) simulation adopted to define the thermal stress distribution in the present LOC package. The numerical calculation shows that when the tape is designed to cover the chip corner, the magnitude of normal stress reveals a maximum value at the edge of the chip.

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Correspondence to Seong-Min Lee.

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Lee, SM. Thermomechanical stability of memory package with LOC structure. Met. Mater. Int. 11, 89 (2005).

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  • plastic package
  • tape design
  • passivation layer
  • stress calculation
  • reliability