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Cycle-based algorithm used to accelerate VHDL simulation

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Abstract

Cycle-based algorithm has very high performance for the simulation of synchronous design, but it is confined to synchronous design and it is not as accurate as event-driven algorithm. In this paper, a revised cycle-based algorithm is proposed and implemented in VHDL simulator. Event-driven simulation engine and cycle-based simulation engine have been imbedded in the same simulation environment and can be used to asynchronous design and synchronous design respectively. Thus the simulation performance is improved without losing the flexibility and accuracy of event-driven algorithm.

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Authors and Affiliations

  1. Department of Computer Science and Technology, Tsinghua University, 100081, Beijing, P. R. China

    Yang Xun

  2. Department of Computer Science and Engineering, Beijing Institute of Technology, 100081, Beijing, P. R. China

    Liu Mingye

Authors
  1. Yang Xun
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  2. Liu Mingye
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Correspondence to Yang Xun.

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Yang, X., Liu, M. Cycle-based algorithm used to accelerate VHDL simulation. J. Comput. Sci. & Technol. 15, 383–387 (2000). https://doi.org/10.1007/BF02948875

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  • DOI: https://doi.org/10.1007/BF02948875

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