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Leakage current estimation of CMOS circuit with stack effect

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Abstract

Leakage current of CMOS circuit increases dramatically with the technology scaling down and has become a critical issue of high performance system. Subthreshold, gate and reverse biased junction band-to-band tunneling (BTBT) leakages are considered three main determinants of total leakage current. Up to now, how to accurately estimate leakage current of large-scale circuits within endurable time remains unsolved, even though accurate leakage models have been widely discussed. In this paper, the authors first dip into the stack effect of CMOS technology and propose a new simple gate-level leakage current model. Then, a table-lookup based total leakage current simulator is built up according to the model. To validate the simulator, accurate leakage current is simulated at circuit level using popular simulator HSPICE for comparison. Some further studies such as maximum leakage current estimation, minimum leakage current generation and a high-level average leakage current macromodel are introduced in detail. Experiments on ISCAS85 and ISCAS89 benchmarks demonstrate that the two proposed leakage current estimation methods are very accurate and efficient.

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Authors and Affiliations

  1. Institute of Computing Technology, The Chinese Academy of Sciences, 10080, Beijing, P.R. China

    Yong-Jun Xu & Xiao-Wei Li

  2. Graduate School of Chinese Academy of Sciences, 100039, Beijing, P.R. China

    Yong-Jun Xu & Xiao-Wei Li

  3. Department of Computer Science and Technology, Tsinghua University, 100084, Beijing, P.R. China

    Zu-Ying Luo & Xian-Long Hong

  4. National ASIC Design Engineering Center, Institute of Automation, The Chinese Academy of Sciences, 100080, Beijing, P.R. China

    Li-Jian Li

Authors
  1. Yong-Jun Xu
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  2. Zu-Ying Luo
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  3. Xiao-Wei Li
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  4. Li-Jian Li
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  5. Xian-Long Hong
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Corresponding author

Correspondence to Yong-Jun Xu.

Additional information

This paper is supported in part by the National Natural Sciences Foundation of China under Grant No.90207002 and in part by the Sci. & Tech. Project of Beijing under Grant No.H020120120130.

Yong-Jun Xu received his B.S. degree in computer communication from Xi'an Institute of Posts & Telecoms in 2001 and then entered Institute of Computing Technology, the Chinese Academy of Sciences (CAS), as a graduate student. He is now a Ph.D. candidate in the institute. His current research intersts include low power design, VLSI/SOC test and verification.

Zu-Ying Luo received his Ph.D. degree from Department of Automation, Tsinghua University in 2001. He is a postdoctoral in Department of Computer Science and Technology, Tsinghua University. His current research interests include low power design, power grid design and optimization.

Xiao-Wei Li received his Ph.D. degree in computer science from Institute of Computing Technology, CAS, in 1991. He worked as an associated professor in Peking University from 1993 to 1995. He is now a professor at Institute of Computing Technology, CAS. His current research interests include low power design, VLSI/SOC design for testability, VLSI/SOC verification and low cost test, and dependable system.

Li-Jian Li received his Ph.D. degree from Institute of Computing Technology, CAS, in July 2001. He is an associate professor of Institute of Automation, CAS. His major interest of research is IC test and design for testability.

Xian-Long Hong was born in 1940. He is a professor at the Department of Computer Science and Technology in Tsinghua University, Beijing, P.R. China. His research interests include layout algorithms and systems.

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Xu, YJ., Luo, ZY., Li, XW. et al. Leakage current estimation of CMOS circuit with stack effect. J. Comput. Sci. & Technol. 19, 708–717 (2004). https://doi.org/10.1007/BF02945598

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  • DOI: https://doi.org/10.1007/BF02945598

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