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A hierarchical reconfiguration strategy for bus-based multiprocessors

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Abstract

A method of providing redundancy to a class of bus—based multiprocessor arrays is discussed. The reconfiguration is hierarchical, providing global spare replacement at the array level and local reconfiguration within the spare block. Results of yield analysis performed on a 32 processor array are presented.

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References

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Authors and Affiliations

  1. VLSI Design Laboratory, Department of Electrical Engineering, McGill University, Montreal, Canada

    Ashish Pancholy, Fidel Muradali & Vinod K. Agarwal

Authors
  1. Ashish Pancholy
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  2. Fidel Muradali
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  3. Vinod K. Agarwal
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Possibly with the help of an external source like a laser.

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Pancholy, A., Muradali, F. & Agarwal, V.K. A hierarchical reconfiguration strategy for bus-based multiprocessors. J. of Compt. Sci. & Technol. 5, 175–186 (1990). https://doi.org/10.1007/BF02943423

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  • DOI: https://doi.org/10.1007/BF02943423

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