Verification of systolic array: An FP functional approach

Abstract

There has been much interest in the use of formal techniques for the design and analysis of systolic arrays. One important aspect of analysis of systolic array is the correctness problem.

A few attempts^[2–4] for the verification of systolic array have appeared in the literature. The deficiency is that all of these methods lack a straightforward way of proving correctness. They need either proposing a solution, then applying inductive techniques or showing that the array satisfies three types of properties: safety, liveness and termination.

In this paper, an FP function l approach is proposed. The goal is to verify that a given systolic design computes the function for which it was intended. Instead of the generation of a systolic architecture, the method generates a system of recursive functional equations which describes the algorithm executed by the architecture. This representation consists of several equations describing processes executed by local cells, equations describing connections between cells, functions representing data streams, and functions describing the relation between the structure of input and output data and the systolic array structures. The minimum solution of the system of recursive functional equations is the function computed by the systolic architecture.

The main advantage of this approach is that it allows us to develop an algebra of functional programs^[1]. We have developed various methods to deal with different kinds of systems of functional recursive equations. By solving the system of recursive functional equations, we can get the least solution directly. This provides a straightforward way for proving correctness.

An example is given. A typical system of recursive functional equations is generated, which can represent most of systolic design. Algebra method is developed showing how to solve this problem.