Abstract
Evolvable hardware (EHW) realizes circuit function through evolution. It may be viewed as the combination of EAs (evolutionary algorithms) and PLDs (programmable logic devices). At present the main problem is that the speed of evolution is too slow. In order to tackle the problem, we must do work from two aspects: algorithm and device structure. This paper presents a function PLD as a new EHW's structure. So the efficiency of coding is improved, and evolution is sped up. A 4-bit comparator is successfully completed.
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References
Hugo de Garis. Evolvable hardware workshop report. Technical Report, ATR, Japan, October 1995
Goldberg D E, Holland J H. Genetic algorithms and machine learning.Machine Learning, 1988,3:95–99
Yao X. A review of evolutionary artificial neural networks.International Journal of Intelligent Systems, 1992b.
Goldberg D E.Genetic algorithms in search, optimization and machine learning. MA: Addison-Wesley, 1989
Boseniuk T, Ebeling W. Evolution strategies in complex optimization: The traveling salesman problem.Systems Analysis Modeling Simulation, 1988,5(5):413–422
Kajitani I, Hoshino T, Iwata M,et al. Variable length chromosome GA for evolvable hardware. InProc. of the 1996IEEE Int. Conf. on Evolutionary Computation.IEEE Press, Piscatawa, NJ, USA, May 1996. 443–447
Qian Bosen. Direct programmable tree structure function.Chinese Journal of Computers, 1996,5:334–341 (in Chinese)
Liu Yong, Kang Lishan, Chen Yuping.Non-numeral Parallel Algorithm. (the second book).Genetic Algorithm. Beijing: Science Press, 1995
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Supported by the National Natural Science Foundation of China
He Wei born in 1969, Ph.D.