Abstract
Noise analysis and avoidance are an increasingly critical step in the design of deep submicron (DSM) integrated circuits (ICs). The crosstalk between neighboring interconnects gradually becomes the main noise sources in DSM ICs. We introduce an efficient and accurate noise-evaluation method for capacitively coupled nets of ICs. The method holds for a victim net with arbitrary number of aggressive nets under ramp input excitation. For common RC nets extracted by electronic design automation (EDA) tools, the deviation between our method and HSPICE is under 10%.
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Chen, B., Yang, H. & Wang, H. Noise estimation for deep sub-micron integrated circuits. Sci China Ser F 44, 396–400 (2001). https://doi.org/10.1007/BF02714742
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DOI: https://doi.org/10.1007/BF02714742