Abstract
Three-dimensional integrated circuit technology with transistors stacked on top of one another in multi-layer silicon film has always been a vision in the future technology direction. While the idea is simple, the technique to obtain high performance multi-layer transistors is extraordinarily difficult. Not until recently does such technology become feasible. In this paper, the background and various techniques to form three-dimensional circuits will be reviewed. Recent development of a simple and promising technology to achieve three-dimensional integration using Metal-Induced-Lateral-Crystallization will be described. Preliminary results of 3D inverters will also be provided to demonstrate the viability for 3D integration.
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Gibbons, J. F., Lee, K. F., One-gate-wide CMOS inverter on laser-recrystallized polysilicon, IEEE Electron Device Lett., vol. EDL-1, June 1980, 117–118.
Chen, C. E., Lam, H. W., Smlhi, S. D. S. et al., Stacked CMOS SRAM cell, IEEE Electron Device Lett., vol. EDL-4, Aug. 1983, 272–274.
Colinge, J. P., Demoulin, E., Lobet, M., Stacked transistors CMOS (ST-MOS), and nMOS technology modified to CMOS, IEEE Trans. Electron Devices, vol. ED-29, Apr. 1982, 585–589.
Kunio, T., Oyama, K., Hayashi, Y. et al., Three-dimensional IC’s, having four stacked active device layers, in IEDM Tech. Dig., 1989, 837–840.
Pae, S., Su, T., Denton, J. P. et al., Multiple layers of silicon-on-insulator islands fabrication by selective epitaxial growth, IEEE Electron Device Letters, 1999, 20(5): 194–196.
Matsumoto, T., Satoh, M., Sakuma, K. et al., New three-dimensional wafer bonding technology using the adhesive injection method Japanese Journal Applied Physics Part 1-Regular Papers Short Notes & Review Papers, 1998, 37(3B): 1217–1221.
Subramanian, V., Toita, M., Ibrahim, N. R. et al., Low-leakage germanium-seeded laterally-crystallized single-grain 100-nm TFT’s for vertical integration applications, IEEE Electron Device Letters, 1999, 20(7): 341–343.
Lee, S. -W., Joo, S. -K. Low temperature poly-Si thin-film transistor fabrication by metal-induced lateral crystallization, IEEE Electron Device Letters, 1996, 17(4): 160–162.
Meng, A., Wang, M., Wong, M., High performance low temperature metal-induced unilaterally crystallized polystalline silicon thin film transistors for system-on-panel applications, IEEE Trans. Electron Devices, Feb. 2000, 47(2): 404–409.
Jin, Z., Moulding, K., Kwok, H. S., The effects of extended heat treatment on Ni induced lateral crystallization of amorphous silicon thin films, IEEE Trans. Electron Devices, 1999, 46(1): 78–82.
Jagar, S., Chan, M., Poon, M. C. et al., SOI formation from amorphous silicon by metal-induced-lateral-crystallization (MILC) and subsequent high temperature annealing, Proceedings of 1999 IEEE International SOI Conference, October 1999, Robnert Park, CA, USA, 1999, 112–113.
Bhat, G. A., Jin, Z., Kwok, H. S. et al., Effects of longitudinal grain boundaries on the performance of MILC-TFT’s, IEEE Electron Device Letter, 1999, 20(2): 97–99.
Palmer, J. E., Thompson, C. V., Smith, H. I., Grain growth and grain size distributions in thin germanium films, J. Appl. Phys., 1987, 62(6): 2492–2497.
Yamauchi, N., Hajjar, J. J., Reif, R., Polysilicon thin-film transistors with channel length and width comparable to or smaller than the grain size of the thin film, IEEE Trans. Electron Devices, 1991, 38(1): 55–59.
Hatalis, M. K., Greve, D. W., High-performance thin-film transistors in low-temperature crystallized LPCVD amorphous silicon films, IEEE Electron Device Letter, 1987, 8(8): 361.
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Chan, M., Ko, P.K. Development of a viable 3D integrated circuit technology. Sci China Ser F 44, 241–248 (2001). https://doi.org/10.1007/BF02714712
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DOI: https://doi.org/10.1007/BF02714712