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A hierarchical approach to instruction-level parallelization

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Abstract

In this paper we extend Percolation Scheduling (PS) to navigate through a hierarchical version of the Control Flow Graph (CFG) representation of a VLIW program. This extension retains the completeness of PS by allowing the “normal” PS transformations to be applied incrementally between adjacent instructions but also enablesnonincremental code motions across arbitrarily large single-entry/single-exit regions of code in constant time. Such nonincremental transformations eliminate the useless code explosions that would otherwise be caused by using incremental transformations to move operations through regions containing multiple control paths and, in conjunction with the hierarchical representation of the CFG, provide a framework for trading offuseful code explosions for increases in parallelism. Simulation results comparing nonincremental with incremental PS are presented.

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This work was supported in part by NSF Grant CCR8704367 and ONR Grant N0001486K0215.

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Novack, S., Nicolau, A. A hierarchical approach to instruction-level parallelization. Int J Parallel Prog 23, 35–62 (1995). https://doi.org/10.1007/BF02577783

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  • DOI: https://doi.org/10.1007/BF02577783

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