Abstract
The mathematical model for the parallelization, or “space-time mapping,” of loop nests is the polyhedron model. The presence ofwhile loops in the nest complicates matters for two reasons: (1) the parallelized loop nest does not correspond to a polyhedron but instead to a subset that resembles a (multidimensional) comb and (2) it is not clear when the entire loop nest has terminated. We describe a communication scheme which can deal with both problems and which can be added to the parallel target loop nest by a compiler.
Similar content being viewed by others
References
M. Griebl and C. Lengauer, On scanning space-time mappedwhile loops. In B. Buchberger and J. Volkert (eds),Parallel Processing: CONPAR '94—VAPP VI, Springer-Verlag, Lecture Notes in Computer Science 854, pp. 677–688 (1994).
C. Lengauer, Loop parallelization in the polytope model. In E. Best (ed.),CONCUR '93, Springer-Verlag, Lecture Notes in Computer Science 715, pp. 398–416 (1993).
M. Griebl and C. Lengauer, A communication scheme for the distributed execution ofwhile loops. Technical Report MIP-9406, Fakultät für Mathematik und Informatik, Universität Passau (June 1994).
E. W. Dijkstra and C. S. Scholten,Predicate Calculus and Program Semantics. Texts and Monographs in Computer Science. Springer-Verlag (1990).
M. Barnett and C. Lengauer, Unimodularity and the parallelization of loops,Parallel Processing Letters,2(2–3):273–281 (1992).
J.-F. Collard, Code generation in automatic parallelizers. In C. Girault, (ed.)Proc. Int. Conf. on Applications in Parallel and Distributed Computing, IFIP W. G., North-Holland 10.3, pp. 185–194, (April 1994).
J. Xue, Automating non-unimodular transformations of loop nests.Parallel Computing,20(5):711–728, May (1994).
M. Griebl and C. Lengauer, On the space-time mapping of WHILE-loops.Parallel Processing Letters,4(3):221–232, (September 1994).
J.-F. Collard, D. Barthou, and P. Feautrier, Fuzzy array dataflow analysis. InProc. 5th ACM SIGPLAN Symp. on Principles & Practice of Parallel Programming (PPoPP). ACM Press (July 1995). To appear. Earlier version: Technical Report TR94-24, LIP, École Normale Supérieure de Lyon (July 1994)
U. Banerjeee,Loop Transformations for Restructuring Compilers: Loop Parallelization. Kluwer (1994).
Y. Wu and T. G. Lewis, Parallelizing while loops. In H. D. Schwetman, (ed.),Int. Conf. on Parallel Processing, Volume II, CRC Press, pp. 1–8 (1990).
Parsytec,PARIX 1.2 Reference Manual (March 1993).
A. Martin. The probe: An addition to communication primitives,Information for Processing Letters,20(3):125–130 (1985).
I. Graham and T. King,The Transputer Handbook. Prentice-Hall (1990).
R. M. Karp, R. E. Miller, and S. Winograd, The organization of computations for uniform recurrence equations.J. ACM,14(3):563–590 (July 1967).
L. Lamport, The parallel execution of DO loops.Comm. ACM,17(2):83–93 (February 1974).
P. Quinton, The systematic design of systolic arrays. In F. F. Soulié, Y. Robert, and M. Tchuente, (eds.),Automata Networks in Computer Science, Chapter 9, pp. 229–260. Manchester University Press, (1987). Also: Technical Reports 193 and 216, IRISA (INRIA-Rennes) (1983).
H. Le Verge, C. Mauras, and P. Quinton. The ALPHA language and its use for the design of systolic arrays.J. VLSI Signal Processing,3:173–182 (1991).
V. van Dongen and M. Petit, PRESAGE: A tool for the parallelization of nested loop programs. In L. J. M. Claesen, (ed.),Formal VLSI Specification and Synthesis (VLSI Design Methods-I), North-Holland, pp. 341–359 (1990).
R. P. Wilson, R. S. French, C. S. Wilson, S. P. Amarasinghe, J. M. Anderson, S. W. K. Tjiang, S.-W., Liao, C.-W. Tseng, M. W. Hall, M. S. Lam, and J. L. Hennessy, Suif: An infrastructure for research on parallelizing and optimizing compilers. InProc. Forth ACM SIGPLAN Symp. on Principles & Practice of Parallel Programming (PPoPP), ACM Press, pp. 31–37 (1994).
M. Wolfe, Experiences with data dependence and loop restructuring in the tiny research tool. Technical Report 90-016, Department of Computer Science and Engineering, Oregon Graduate Institute of Science and Technology (1990).
M. Raji-Werth and P. Feautrier, On parallel program generation for massively parallel architectures. In M. Durand and F. El Dabaghi, (eds.),High Performance Computing II. North-Holland (1991).
P. Boulet, M. Dijon, E. Lequiniou, and T. Risset. Reference manual of the bouclettes parallelizer. Technical Report 94-04, LIP, École Normale Supérieure de Lyon (October 1994).
L. Rauchwerger and D. Padua, Parallelizing while loops for multiprocessor systems. InProc. 9th Int. Parallel Programming Symposium (IPPS'95), IEEE Computer Society Press. pp. 347–355 (1995).
P. P. Tirumalai, M. Lee, and M. S. Schlansker, Parallelization of while loops on pipelined architectures.J. Supercomputing,5:119–136, 1991.
J.-F. Collard, Automatic parallelization ofwhile-loops using speculative execution.Int. J. Parallel Programming, (1995). To appear. Earlier version:Proc. 1994Scalable High Performance Computing Conf., IEEE, pp. 429–436, (May 1994).
C. Lengauer and M. Griebl, On the parallelization of loop nests containingwhile loops. In N. N. Mirenkov, Q.-P. Gu, S. Peng, and S. Sedukhin, (eds.),Proc. 1st Aizu Int. Symp. on Parallel Algorithm/Architecture Synthesis (pAs'95), IEEE Computer Society Press pp. 10–18 (1995).
Author information
Authors and Affiliations
Additional information
This work has been presented in part at the conference CONPAR 94-VAPP VI (see Ref. 1)
Rights and permissions
About this article
Cite this article
Griebl, M., Lengauer, C. A communication scheme for the distributed execution of loop nests withwhile loops. Int J Parallel Prog 23, 471–496 (1995). https://doi.org/10.1007/BF02577774
Received:
Issue Date:
DOI: https://doi.org/10.1007/BF02577774