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Artificial Life and Robotics

, Volume 3, Issue 3, pp 170–175 | Cite as

Implementation of multilayer neural network with threshold neurons and its analysis

  • Kazuo Sato
  • Hiroomi Hikawa
Original Article

Abstract

In this paper, the implementation of new digital architecture for a multilayer neural network (MNN) with on-chip learning is discussed. The advantage of using the digital approach is that it can use state-of-the-art VLSI and ULSI implementation techniques. One of the major hard-ware problems in implementing a neural network is the activating function of the neurons. The proposed MNN uses a simple function as the neuron's activating function to reduce the circuit size. Moreover, the proposed MNN has an on-chip learning capability. As the learning algorithm, a backpropagation algorithm is modified for effective hard-wave implementation. The proposed MNN is implemented on a field-programmable gate array (FPGA) to evaluate the learning performance and circuit size.

Key words

Multilayer neural network On-chip learning Back propagation algorithm 

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References

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    White BA, Elmasry MI (1992) The digi-neocognitron: a digital neocognitron neural network model for VLSI. IEEE Trans Neural Networks 3:73–85CrossRefGoogle Scholar
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    Lehmann C, Viredaz M, Blayo F (1993) (A generic systolic array building block for neural networks with on-chip learning. IEEE Trans Neural Networks 4(3)Google Scholar
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    Hikawa H (1997) Learning performance of multilayer neural network with threshold neurons, ITC-CSCC'97, vol. II, pp 1065–1068Google Scholar
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    Hikawa H (1995) Implementation of simplified multilayer neural networks with on-chip learning. IEEE ICNN'95, vol 4, pp 1633–1637Google Scholar

Copyright information

© ISAROB 1999

Authors and Affiliations

  1. 1.Department of Computer Science and Intelligent SystemsOita UniversityOitaJapan

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