Implementing division with field programmable gate arrays

  • Marianne E. Louie
  • Milos D. Ercegovac


This article presents a method to map digit-recurrence arithmetic algorithms to lookup-table based Field Programmable Gate Arrays (FPGAs). By reducing the number of binary inputs to combinational logic and merging algorithm steps, the strategy creates new simplified functions to decrease logic depth and area. To illustrate this method, a radix-2 digit-recurrence division algorithm is mapped to the Xilinx XC4010, a lookup-table based FPGA. The mapping develops a linear sequential array design that avoids the common problem of large fanout delay in the critical path. This approach has a cycle time independent of precision while requiring approximately the same number of logic blocks as a conventional design.


Field Programmable Gate Array Critical Path Logic Level Combinational Logic Logic Block 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Kluwer Academic Publishers 1994

Authors and Affiliations

  • Marianne E. Louie
    • 1
  • Milos D. Ercegovac
    • 1
  1. 1.Computer Science DepartmentUniversity of CaliforniaLos Angeles

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