Skip to main content

Characterization of subthreshold MOS mismatch in transistors for VLSI systems

Abstract

MOS transistor mismatch is revisited in the context of subthreshold operation and VLSI systems. We report experimental measurements from large transistor arrays with device sizes typical for digital and analog VLSI systems (areas between 9 and 400μm2). These are fabricated at different production qualified facilities in 40-nm gate oxide,n-well andp-well, mask lithography processes. Within the small area of our test-strips (3 mm2), transistor mismatch can be classified into four categories: random variations, “edge,” “striation,” and “gradient” effects. The edge effect manifests itself as a dependence of the transistor current on its position with reference to the surrounding structures. Contrary to what was previously believed, edge effects extend beyond the outer most devices in the array. The striation effect exhibits itself as a position-dependent variation in transistor current following a sinusoidal oscillation in space of slowly varying frequency. The gradient effect is also a position-dependent spatial variation but of much lower frequency. When systematic effects are removed from the data, the random variations follow an inverse linear dependence on the square root of transistor area.

This is a preview of subscription content, access via your institution.

References

  1. R.M. Swanson and J.D. Meindl, “Ion-implanted complementary MOS transistors in low-voltage circuits,”IEEE J. Solid-State Circuits, Vol. SC-7, No. 2, pp. 146–173, 1972.

    Article  Google Scholar 

  2. E.A. Vittoz, “Micropower techniques,” inVLSI Circuits for Telecommunications (Y.P. Tsividis and P. Antognetti, eds.), Prentice Hall: Englewood Cliffs, NJ, 1985.

    Google Scholar 

  3. E.A. Vittoz and J. Fellrath, “CMOS analog integrated circuits based on weak inversion operation,”IEEE J. Solid-State Circuits, Vol. SC-12, No. 3, pp. 224–231, 1977.

    Article  MATH  Google Scholar 

  4. E.A. Vittoz, “The design of high-performance analog circuits on digital CMOS chips,”IEEE J. Solid-State Circuits, Vol. SC-20, No. 3, pp. 657–665, 1985.

    Article  Google Scholar 

  5. J. Burr and A. Peterson, “Ultra low power CMOS technology,”Proc. 3rd NASA Symp. VLSI Design, Boise, ID, 1991.

  6. C.A. Mead,Analog VLSI and Neural Systems, Addison-Wesley: Reading, MA, 1989.

    Book  MATH  Google Scholar 

  7. E.A. Vittoz, “Future of analog in the VLSI environment,”Proc. 1990 Int. Symp. Circuits and Systems, pp. 1372–1375, New Orleans, 1990.

  8. A.G. Andreou and K.A. Boahen, “Neural Information Processing II,” inAnalog VLSI: Signal and Information Processing (M. Ismail and T. Fiez, eds.), McGraw-Hill: New York, 1994.

    Google Scholar 

  9. R.W. Keyes, “Physical limits in digital electronics,”Proc. IEEE, Vol. 63, No. 5, pp. 740–767, 1975.

    Article  Google Scholar 

  10. R.W. Keyes,The Physics of VLSI Systems, Addison-Wesley: Wokingham, England, 1987.

    Google Scholar 

  11. C.A. Mead and L. Conway,Introduction to VLSI Systems, Addison-Wesley: Reading, MA, 1981.

    Google Scholar 

  12. J.B. Shyu, G.C. Temes, and K. Yao, “Random errors in MOS capacitors,”IEEE J. Solid-State Circuits, Vol. SC-17, No. 6, 1982.

  13. M.J. Pelgrom, A.C.J. Kuinmaijer, and A.P.G. Welbers, “Matching properties of MOS transistors,”IEEE J. Solid-State Circuits, Vol. SC-24, No. 5, 1989.

  14. J.B. Shyu, G.C. Temes, and F. Krummenacher, “Random error effects in matched MOS capacitors and current sources,”IEEE J. Solid-State Circuits, Vol. SC-19, No. 6, 1984.

  15. K.R. Lakshmukumar, R.A. Hadaway, and M.A. Copeland, “Characterization and modeling of mismatch in MOS transistors for precision analog design,”IEEE J. Solid-State Circuits, Vol. SC-21, No. 6, 1986.

  16. K.A. Boahen and A.G. Andreou, “A contrast sensitive silicon retina with reciprocal synapses,” inAdvances in Neural Information Processing Systems 4 (J.E. Moody, S.J. Hanson, and R.P. Lippmann, eds.), Morgan Kaufmann: San Mateo, CA, 1992.

    Google Scholar 

  17. M.G. Buehler, B.R. Blaes, H.R. Sayah, and U. Lieneweg, “Parameter distributions for complex VLSI circuits,”Proc. Decennial Caltech Conf. VLSI, MIT Press, 1989.

  18. M. Godfrey, “CMOS device modeling for subthreshold circuits,”IEEE Trans. Circuits Systems II, Vol. 39, No. 8, 1992.

    Google Scholar 

  19. A. Pavasović, A.G. Andreou, and C.R. Westgate, “Characterization of CMOS process variations by measuring subthreshold current,”Non-Destructive Characterization of Materials, Vol. IV (C.O. Ruud and R.E. Green, eds.), Plenum Press: New York, 1991.

    Google Scholar 

  20. A. Pavasović,Subthreshold Region MOSFET Mismatch Analysis and Modeling for Analog VLSI Systems, Ph.D. dissertation, The Johns Hopkins University, Baltimore, 1991.

    Google Scholar 

  21. S. Wolfram,Mathematica, A System for Doing Mathematics by Computer, Addison-Wesley: Reading, MA, 1988.

    MATH  Google Scholar 

  22. J. Tanner,Integrated Optical Motion Detection, Ph.D. dissertation, California Institute of Technology, 1986.

  23. C.A. Mead, Personal communication.

  24. G.J. Hahn and S.S. Shapiro,Statistical Models in Engineering, Wiley: New York, 1967.

    Google Scholar 

  25. J. Rijmenants, J.B. Litsios, T.R. Schwarz, and M.G.R. Degrauwe, “ILAC: an automated layout tool for analog CMOS circuits,”IEEE J. Solid-State Circuits, Vol. SC-24, No. 2, 1989.

  26. Y. Tsividis, “Problems with precision modeling of analog MOS LSI,”Proc. IEEE Int. Electron Devices Meeting, San Francisco, pp. 274–277, 1982.

  27. A.G. Andreou, “In-situ characterization of carrier mobility in field effect transistors,” inReview of Progress in Quantitative Nondestructive Evaluation 8B (D.O. Thompson and D.E. Chimenti, eds.), Plenum Press: New York, pp. 1247–1254, 1989.

    Chapter  Google Scholar 

  28. K. Yang, R.C. Meitzler, A.G. Andreou, “A model for MOS effective channel mobility with emphasis in the subthreshold and transition region,”Proceedings IEEE ISCAS-94, London, June 1994.

  29. J.T.C. Chen and R.S. Muller, “Carrier mobilities at weakly inverted silicon surfaces,”J. Appl. Phy., Vol. 45, No. 2, 1974.

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and Permissions

About this article

Cite this article

Pavasović, A., Andreou, A.G. & Westgate, C.R. Characterization of subthreshold MOS mismatch in transistors for VLSI systems. Journal of VLSI Signal Processing 8, 75–85 (1994). https://doi.org/10.1007/BF02407112

Download citation

  • Received:

  • Revised:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF02407112

Keywords

  • Test Strip
  • Density Plot
  • Subthreshold Region
  • VLSI System
  • Analog Circuit Design