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Computing

, Volume 39, Issue 3, pp 187–199 | Cite as

An orthogonal systolic array for the algebraic path problem

  • Y. Robert
  • D. Trystram
Contributed Papers

Abstract

This paper is devoted to the design of an orthogonal systolic array ofn(n+1) elementary processors which can solve any instance of the Algebraic Path Problem within only 5n−2 time steps, and is compared with the 7n−2 time steps of the hexagonal systolic array of Rote [8].

AMS Subject Classifications

68A05 (05C35, 05C38, 16A78, 65F05, 68E10) 

General terms

Algorithms design performance 

CR Categories and Subjet Descriptors

C.1.2 [processor architectures]

multiple data stream architectures (multiprocessors) — systolic arrays

G.1.0 [numerical analysis]

general-parallel algorithms

G.1.3 [numerical analysis]

numerical linear algebra-matrix inversion

G.2.2 [discrete mathematics]

graph theory-path problems

B.6.1 [logic design]

design styles-cellular arrays

B.7.1 [integrated circuits]

types and design styles-algorithms implemented in hardware

VLSI

(very large scale integration)

Ein orthogonales systolisches Feld für das algebraische Wegproblem

Zusammenfassung

Es wird ein orthogonales systolisches Feld (systolic array) mitn(n+1) einfachen Prozessoren entworfen, das das algebraische Wegproblem in nur 5n−2 Schritten lösen kann, im Vergleich zu 7n−2 Schritten beim hexagonalen systolischen Feld von Rote [8].

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References

  1. [1]
    Ahmed, H. M., Delosme, J. M., Morf, M.: Highly concurrent computing structures for matrix arithmetic and signal processing. Computer15/1, 65–82 (1982).Google Scholar
  2. [2]
    Delosme, J. M.: Algorithms for finite shift-rank processes. Ph.D. Thesis, Technical Report M735-22, Sept. 1982, Stanford Electronics Laboratories.Google Scholar
  3. [3]
    Guibas, L. J., Kung, H. T., Thompson, C. D.: Direct VLSI implementation of combinatorial algorithms, pp. 509–525. Proc. Caltech Conf. on VLSI: Architecture, design, fabrication, Calfornia Institute of technology, Pasadena (1979).Google Scholar
  4. [4]
    Kung, H. T.: Why systolic architectures. Computer15/1, 37–46 (1982).Google Scholar
  5. [5]
    Kung, H. T., Lam, M. S.: Fault-tolerance and two-level pipelining in VLSI systolic arrays. Journal of Parallel and Distributed Computing1/1, 32–63 (1984).Google Scholar
  6. [6]
    Kung, H. T., Leiserson, C. E.: Systolic Arrays (for VLSI). In: Proc. of the Symposium on Sparse Matrices Computations, pp. 256–282 (Duff, I. S., Stewart, G. W., eds.). Knoxville, Tenn. (1978).Google Scholar
  7. [7]
    Robert, Y.: Block LU decomposition of a band matrix on a systolic array. Int. J. Computer Math.17, 295–315 (1985).Google Scholar
  8. [8]
    Rote, G.: A systolic array algorithm for the algebraic path problem (shortest paths; matrix inversion). Computing34, 191–219 (1985).CrossRefMATHMathSciNetGoogle Scholar
  9. [9]
    Rote, G.: A systolic array for the algebraic path problem (which includes the inverse of a matrix and the shortest distances in a graph). Rechenzentrum Graz, Austria, Bericht RZG-101 (1984).Google Scholar
  10. [10]
    Zimmermann, U.: Linear and combinatorial optimization in ordered algebraic structures. Ann. Discrete Math.10, 1–380 (1981).Google Scholar

Copyright information

© Springer-Verlag 1987

Authors and Affiliations

  • Y. Robert
    • 1
  • D. Trystram
    • 2
  1. 1.CNRS, Laboratoire TIM 3Grenoble UniversitéSaint Martin d'Hères, CedexFrance
  2. 2.Ecole Centrale ParisChatenay Malabry, CedexFrance

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