High-level optimizations in compiling process descriptions to asynchronous circuits

  • Ganesh Gopalakrishnan
  • Venkatesh Akella
Article

Abstract

Asynchronous/Self-Timed designs are beginning to attract attention as promising means of dealing with the complexity of modern VLSI technology. In this article, we present our views on why asynchronous systems matter. We then present details of our high level synthesis tool SHILPA that can automatically synthesize asynchronous circuits from descriptions in our concurrent programming language,hopCP. We outline many of the novel features of hopCP and also sketch how these constructs are compiled into asynchronous circuits, and then focus on the high level optimizations employed by SHILPA, includingconcurrent guard evaluation and concurrent process decomposition.

Keywords

Process Definition Asynchronous Circuit Barrier Synchronization Choice Node Synchronous Circuit 

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Copyright information

© Kluwer Academic Publishers 1994

Authors and Affiliations

  • Ganesh Gopalakrishnan
    • 1
  • Venkatesh Akella
    • 2
  1. 1.Department of Computer ScienceUniversity of UtahSalt Lake City
  2. 2.Department of Electrical and Computer EngineeringUniversity of CaliforniaDavis

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