A chip set for pipeline and parallel pipeline FFT architectures

  • V. Szwarc
  • L. Desormeaux
  • W. Wong
  • C. P. S. Yeung
  • C. H. Chan
  • T. A. Kwasniewski


A chip set for pipelined and parallel pipelined FFT applications is presented. The set consists of two cascadeable chips with built-in self-test and a chip-interconnectivity test feature. The two ASICs are a 15k gate Complex-Butterfly and a 9k gate FFT Switch. The Complex-Butterfly uses redundant binary arithmetic (RBA), a modified Booth algorithm and a Wallace tree architecture to achieve a throughput of better than 25 Msamples/sec. The cascadeable FFT Switch is designed to support the implementation of radix-2, 2 N point, pipeline FFTs. Both devices have been fabricated in 1.5μm CMOS gate array technology.


Systolic Array Pipeline Stage Linear Feedback Shift Register Master Clock Twiddle Factor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Kluwer Academic Publishers 1994

Authors and Affiliations

  • V. Szwarc
    • 1
  • L. Desormeaux
    • 1
  • W. Wong
    • 2
  • C. P. S. Yeung
    • 2
  • C. H. Chan
    • 2
  • T. A. Kwasniewski
    • 2
  1. 1.Communications Research CenterCommunications CanadaOttawaCanada
  2. 2.Department of ElectronicsCarleton UniversityOttawaCanada

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