Mathematical systems theory

, Volume 21, Issue 1, pp 85–98 | Cite as

Minimum-diameter cyclic arrangements in mapping data-flow graphs onto VLSI arrays

  • P. Erdös
  • I. Koren
  • S. Moran
  • G. M. Silberman
  • S. Zaks


Regular arrays of processing elements in VLSI have proved to be suitable for high-speed execution of many matrix operations. To execute an arbitrary computational algorithm on such processing arrays, it has been suggested mapping the given algorithm directly onto a regular array. The computational algorithm is represented by a data-flow graph whose nodes are to be mapped onto processors in the VLSI array.

This study examines the complexity of mapping data-flow graphs onto square and hexagonal arrays of processors. We specifically consider the problem of routing data from processors in a given (source) sequence to another (target) sequence.

We show that under certain conditions, the above problem is equivalent to the one of finding a minimum-diameter cyclic arrangement. The complexity of the latter problem is analyzed and upper and lower bounds on the number of intermediate rows of processors (between the source and target rows) are derived.


Mapping Process Mapping Problem Hexagonal Array Processor Array Cyclic Shift 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag New York Inc 1988

Authors and Affiliations

  • P. Erdös
    • 1
  • I. Koren
    • 2
  • S. Moran
    • 3
  • G. M. Silberman
    • 3
  • S. Zaks
    • 3
  1. 1.Mathematical Institute of the Hungarian Academy of SciencesBudapestHungary
  2. 2.Department of Electrical and Computer EngineeringUniversity of MassachusettsAmherstUSA
  3. 3.Department of Computer ScienceTechnion-Israel Institute of TechnologyHaifaIsrael

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