Abstract
A systematic method for the mapping of digital filter algorithms onto systolic hardware is presented. The method is based on thez-domain characterization of the required filter. It yields filter structures that are modular, pipelined, and hierarchical, and can be used to obtain multidimensional structures. All the structures discussed have a latency of one sampling period and some have maximum concurrency. The paper also deals with the problems of line and frame wrap-around that are inherent in raster-scanned images and ways are suggested for their elimination.
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Sunder, S., El-Guibaly, F. & Antoniou, A. Systolic implementation of digital filters. Multidim Syst Sign Process 3, 63–78 (1992). https://doi.org/10.1007/BF01941018
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DOI: https://doi.org/10.1007/BF01941018