Abstract
The GVIP (geometric and TV image processor) graphics processor, which creates and synthesizes computer graphics and TV images and meets the requirements of multi-media systems, is described. The hardware modules that make up this graphics processor include: a 32-bit embedded RISC processor, a Phong and Gouraud shading processor, a texture mapping processor, a hidden surface removal processor, an HDTV video image processor, a BitBlt processor, an imageprocessing module, and an outline font fill generator. These hardware modules fabricated using 0.8 μm CMOS standard cells have been placed in three integrated circuit chips. The total number of gates used for one set of chips is approximately 350000.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Ishihata Ineno, Hovi, et al (1990) Architecture of CAPII and memory system. Technical report. Comput Architect IPSJ 83–87: 83–97
Sasaki S (1993) 3-Dimensional graphics accelerater SUB-ARU. NIKKEI ELECTRONICS: 578:148–151
Fuchs H (1988) An introduction to pixel-plane and VLSI-intensive graphics systems. In: Theoretical foundation of computer graphics and CAD, Springer, Berlin Heidelberg New York, pp 675–688
Jayasinghe JAKS, Herrmann OE (1991) Two level pipeline of systolic array graphics engines. In: Advances in computer graphics hardware IVI. Springer, Berlin Heidelberg New York, 133–148
Akeley K (1989) The silicon graphics 4D/240 GTX Superworkstation. CG&A 9:71–83
Ikedo T (1977) Patent S53-110331 (Japan)
Ikedo T (1984) High speed techniques for a 3D color graphics terninal. IEEE CG&A 4(5):46–58
Carinalli C, et al (1989) National's advanced graphics chips set for high-performance graphics. IEEE CG&A 6(10):40–48
Jackel D (1991) A real-time raster scan display for 3D graphics. Advances in Hardware IV. Springer, Berlin Heidelberg New York, pp 213–227
Poulton J, et al (1992) Breaking the frame buffer bottleneck with logic-enhanced memories. IEEE CG&A 12(6):65–74
Sproul F, Sutherland IE, Thompson A, Gupta S, Mint C (1983) The 8 by 8 display. ACM Trans Graphics 2:32–56
Ikedo T (1983) Patent S58-24419 (Japan)
Goris A, et al (1987) A configurable pixel cache for fast image generation. IEEE CG & A 7(3):24–32
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Ikedo, T. A scalable high-performance graphics processor: GVIP. The Visual Computer 11, 121–133 (1995). https://doi.org/10.1007/BF01898598
Issue Date:
DOI: https://doi.org/10.1007/BF01898598